公开(公告)号：US08716093B2

公开(公告)日：2014-05-06

申请号：US13428900

申请日：2012-03-23

Applicant: Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

Inventor： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC: H01L21/336 ,  H01L21/338 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Abstract translation: 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US20120329252A1

公开(公告)日：2012-12-27

申请号：US13529564

申请日：2012-06-21

Applicant: WonSeok Yoo ,  Nam-Kyu Kim ,  Bonghyun Kim ,  Seung Hun Lee ,  Heedon Hwang

Inventor： WonSeok Yoo ,  Nam-Kyu Kim ,  Bonghyun Kim ,  Seung Hun Lee ,  Heedon Hwang

IPC: H01L21/20

CPC classification number: H01L29/045 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66636

Abstract: A semiconductor device may include a semiconductor substrate with an active region, a gate line disposed on the active region, an epitaxial pattern disposed on the semiconductor substrate beside the gate line, the epitaxial pattern including a semiconductor material different from the semiconductor substrate, and a capping pattern disposed on the epitaxial pattern. The capping pattern may improve contact with contact plug and may reduce variation in mean ion depths of an associated field effect transistor.

Abstract translation: 半导体器件可以包括具有有源区的半导体衬底，设置在有源区上的栅极线，设置在栅极线旁边的半导体衬底上的外延图案，该外延图案包括不同于半导体衬底的半导体材料，以及 设置在外延图案上的封盖图案。 封盖图案可以改善与接触塞的接触，并且可以减小相关的场效应晶体管的平均离子深度的变化。

公开(公告)号：US20120142159A1

公开(公告)日：2012-06-07

申请号：US13242302

申请日：2011-09-23

Applicant: Tae-Gon Kim ,  Sang-Bom Kang ,  Jae-Young Park ,  Kang-Hun Moon ,  Hyun-Jun Sim ,  Seung-Hun Lee ,  Han-Ki Lee ,  Hyun-Seung Kim

Inventor： Tae-Gon Kim ,  Sang-Bom Kang ,  Jae-Young Park ,  Kang-Hun Moon ,  Hyun-Jun Sim ,  Seung-Hun Lee ,  Han-Ki Lee ,  Hyun-Seung Kim

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/26586 ,  H01L21/2257 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Methods for fabricating a semiconductor device are provided wherein, in an embodiment, the method includes the steps of forming a gate electrode on a semiconductor substrate, forming a trench by recessing the semiconductor substrate in the vicinity of the gate electrode, doping an anti-diffusion ion into a portion of the semiconductor substrate in the trench, and growing an impurity-doped epitaxial layer on the semiconductor substrate doped with the anti-diffusion ion.

Abstract translation: 提供了制造半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在半导体衬底上形成栅电极，通过在栅极附近凹入半导体衬底形成沟槽，掺杂抗扩散 离子进入沟槽中的半导体衬底的一部分，并且在掺杂有抗扩散离子的半导体衬底上生长杂质掺杂的外延层。

公开(公告)号：US20100194712A1

公开(公告)日：2010-08-05

申请号：US12566411

申请日：2009-09-24

Applicant: Keon Joon Ahn ,  Jae Dong Kim ,  Jong Uk Kim ,  Sang IL Park ,  Seung Hun Lee ,  Hyun Youl Lee

Inventor： Keon Joon Ahn ,  Jae Dong Kim ,  Jong Uk Kim ,  Sang IL Park ,  Seung Hun Lee ,  Hyun Youl Lee

IPC: G06F3/042

CPC classification number: H03K17/9631 ,  G06F3/042 ,  H03K2217/96042

Abstract: Disclosed herein is an optical pointing device as a user interface for electronic devices such as communication terminals and the like. The optical pointing device includes a light receiving part, an optical unit transferring light to the light receiving part and including a reflection part disposed in an optical path, a frame body integrally formed with the reflection part to support the reflection part, a cover covering the frame body and having an interface surface, and a light source illuminating the cover. The optical pointing device reduces the number of components and permits convenient and easy assembly, thereby significantly improving productivity while reducing assembly defect.

Abstract translation: 这里公开了作为用于诸如通信终端等的电子设备的用户界面的光学指向设备。 光学指向装置包括光接收部分，光学单元，其将光传输到光接收部分并且包括设置在光路中的反射部分，与反射部分一体地形成以支撑反射部分的框体，覆盖 框体并具有界面，以及照明该盖的光源。 光学指向装置减少了部件的数量并且允许方便和容易的组装，从而显着地提高生产率，同时减少组装缺陷。

公开(公告)号：US07480194B2

公开(公告)日：2009-01-20

申请号：US11610212

申请日：2006-12-13

Applicant: Seung Hun Lee

Inventor： Seung Hun Lee

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C5/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093

Abstract: A data I/O apparatus for use in a memory device. The data I/O apparatus for use in the memory device performs data transmission using the same polarity when neighbor global I/O lines have opposite polarities to reduce coupling noise generated between global I/O lines acting as data I/O lines of a memory device, performs data recovery, and basically deletes the coupling noise, such that it reduces the failure rate of the memory device.

Abstract translation: 一种用于存储装置的数据I / O装置。 当相邻全局I / O线具有相反的极性时，用于存储装置的数据I / O装置使用相同的极性执行数据传输，以减少作为充当存储器的数据I / O线的全局I / O线之间产生的耦合噪声 设备，执行数据恢复，并基本上删除耦合噪声，从而降低存储器件的故障率。

公开(公告)号：US20060160634A1

公开(公告)日：2006-07-20

申请号：US11176554

申请日：2005-07-06

Applicant: Seung-Hun Lee

Inventor： Seung-Hun Lee

IPC: A63B69/36

CPC classification number: A63B69/3617 ,  A63B53/04 ,  A63B53/08 ,  A63B69/3685 ,  A63B2053/0416 ,  A63B2071/0625 ,  A63B2071/0627 ,  A63B2071/0633

Abstract: The present invention relates to a golf club for exercise, with the help of which a golfer can confirm the site on a club head impacted on a ball easily through the sense during swinging practice so as to correct or improve the swinging posture and the impact exactness. Thus, a golf club (G) comprising a grip (10), a shaft (20) and a head (30) for hitting balls, wherein the golf club further includes a due hitting part (31) providing an ideal hitting spot, the due hitting part protruding from and integrally with the face of the head in accordance with the sweet spot; and a cushion member (40) provided with a fitting opening (41) for receiving the due hitting part (31), the cushion member being attached to the face of the head, is provided by the invention (FIG. 2).

Abstract translation: 本发明涉及一种用于运动的高尔夫球杆，借助于此，高尔夫球手可以通过该摆动练习中的感觉容易地确认球杆头上撞击球的位置，从而校正或改善摆动姿势和冲击精度 。 因此，高尔夫球杆（G）包括用于击球的把手（10），轴（20）和头（30），其中高尔夫球杆还包括提供理想击球点的适当击打部分（31）， 根据甜点，使头部的表面突出并与其整体一致; 以及缓冲构件（40），其设置有用于接收所述击打部分（31）的装配开口（41），所述缓冲构件附接到所述头部的所述面部，由本发明（图2）提供。

公开(公告)号：US06298001B1

公开(公告)日：2001-10-02

申请号：US08636428

申请日：1996-04-23

Applicant: Seung-hun Lee ,  Tae-jin Kim

Inventor： Seung-hun Lee ,  Tae-jin Kim

IPC: G11C1700

CPC classification number: G11C29/48 ,  G11C29/50 ,  G11C2029/5004 ,  Y10T307/615

Abstract: A semiconductor memory device for a package-state voltage test has a plurality of bonding pads that are electrically connected to an external device in a package state, at least one internal DC voltage generator, at least one switch connected between one of the bonding pads and the internal DC voltage generator. The switch is on during a test mode and is off during a normal mode. The switch controller is connected between at least two of the plurality of bonding pads and serves to control the switch in response to an external switching signal in the test mode. Because of this design, a number of DC voltage tests can be performed without increasing chip size since a general control pad also serves as a DC voltage test pad.

Abstract translation: 一种用于封装状态电压测试的半导体存储器件，具有与封装状态的外部器件电连接的多个接合焊盘，至少一个内部直流电压发生器，至少一个开关，其连接在一个焊盘和 内部直流电压发生器。 开关在测试模式下打开，并在正常模式下关闭。 开关控制器连接在多个接合焊盘中的至少两个接合焊盘之间，用于响应于测试模式中的外部开关信号来控制开关。 由于这种设计，可以在不增加芯片尺寸的情况下执行多个直流电压测试，因为通用控制板也用作直流电压测试板。

公开(公告)号：US5646899A

公开(公告)日：1997-07-08

申请号：US575714

申请日：1995-12-20

Applicant: Hyun-Soon Jang ,  Seung-Hun Lee

Inventor： Hyun-Soon Jang ,  Seung-Hun Lee

IPC: G11C11/409 ,  G11C7/06 ,  G11C7/22 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/065

Abstract: A bit line sensing circuit of a semiconductor memory device is disclosed which includes a pull-up control signal generator that enables the peak current to be small by supplying to the P sense amplifier a pull-up voltage of the low level in an initial sensing process. When the peak current is stabilized, the pull-up control signal generator then reduces the time required for raising the pull-up voltage by very quickly raising the voltage of the pull-up control signal. This results in the advantages that the peak current can be greatly reduced without slowing sensing speed, and voltage noise caused from peak currents can be eliminated.

Abstract translation: 公开了一种半导体存储器件的位线感测电路，其包括上拉控制信号发生器，其通过在初始感测过程中向P读出放大器提供低电平的上拉电压来使峰值电流变小 。 当峰值电流稳定时，上拉控制信号发生器通过非常快速地提高上拉控制信号的电压来减少提高上拉电压所需的时间。 这导致了峰值电流可以大大降低而不减慢感测速度的优点，并且可以消除由峰值电流引起的电压噪声。

公开(公告)号：US09577043B2

公开(公告)日：2017-02-21

申请号：US14826174

申请日：2015-08-13

Applicant: Jongryeol Yoo ,  Hyun Jung Lee ,  Sunjung Kim ,  Seung Hun Lee ,  Eunhye Choi

Inventor： Jongryeol Yoo ,  Hyun Jung Lee ,  Sunjung Kim ,  Seung Hun Lee ,  Eunhye Choi

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823412 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium. A germanium concentration difference between the first and second channel layers is greater than a germanium concentration difference between the buffer layer and the second channel layer. The spacer layer has a germanium concentration gradient.

Abstract translation: 半导体器件包括在半导体衬底上的包括第一和第二区域的缓冲层，第一区域的缓冲层上的第一沟道层，第二区域的缓冲层上的第二沟道层以及第二区域之间的间隔层 通道层和缓冲层。 缓冲层，第一和第二沟道层以及间隔层由包括锗的半导体材料形成。 第一和第二沟道层之间的锗浓度差大于缓冲层和第二沟道层之间的锗浓度差。 间隔层具有锗浓度梯度。

公开(公告)号：US20160218181A1

公开(公告)日：2016-07-28

申请号：US14968049

申请日：2015-12-14

Applicant: Moon Seung Yang ,  Eun Hye Choi ,  Sun Jung Kim ,  Seung Hun Lee ,  Hyun-Jung Lee

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Sun Jung Kim ,  Seung Hun Lee ,  Hyun-Jung Lee

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L29/161 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

Abstract translation: 提供半导体衬底和半导体器件。 半导体衬底包括基底衬底，在基底衬底上的第一硅锗层和第一硅锗层上的第二硅锗层。 第二硅锗层的锗部分在远离基底的方向上减小，并且第二硅锗层的最下部分的锗部分大于第一硅锗层的最上部的锗部分。