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    Chip carrier for semiconductor chip
    11.
    发明授权
    Chip carrier for semiconductor chip 有权
    半导体芯片芯片载体

    公开(公告)号：US07102239B2

    公开(公告)日：2006-09-05

    申请号：US10909029

    申请日：2004-07-30

    Applicant: Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

    Inventor： Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

    IPC: H01L23/48

    CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15311

    Abstract: A chip carrier for a semiconductor chip is provided. A plurality of solder pads for bump soldering are formed on a chip mounting surface of the chip carrier, to allow a flip chip to be mounted and electrically connected to the chip carrier. A solder mask layer is formed on the chip carrier, wherein a plurality of openings are provided in the solder mask layer to expose the solder pads, and an outwardly opening extended portion is formed respectively from the openings corresponding to the solder pads having a relatively narrower pitch therebetween, so as to prevent formation of voids during an underfill process for filing a gap between the flip chip and the chip carrier.

    Abstract translation: 提供了一种用于半导体芯片的芯片载体。 在芯片载体的芯片安装表面上形成用于凸块焊接的多个焊盘，以允许倒装芯片安装并电连接到芯片载体。 在芯片载体上形成焊料掩模层，其中在焊料掩模层中设置多个开口以露出焊盘，并且从对应于具有相对较窄的焊盘的开口分别形成向外开口的延伸部分 间隔，以防止在底部填充过程中形成空隙，以便在倒装芯片和芯片载体之间填充间隙。

    Heat-dissipating structure and heat-dissipating semiconductor package having the same
    12.
    发明授权
    Heat-dissipating structure and heat-dissipating semiconductor package having the same 有权
    散热结构及其散热半导体封装

    公开(公告)号：US07863731B2

    公开(公告)日：2011-01-04

    申请号：US12001612

    申请日：2007-12-11

    Applicant: Chin-Te Chen ,  Ke-Chuan Yang ,  Chang-Fu Lin

    Inventor： Chin-Te Chen ,  Ke-Chuan Yang ,  Chang-Fu Lin

    IPC: H01L23/10

    CPC classification number: H01L23/367 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via a thermal interface material, such as a solder material, wherein a groove is formed on the heat sink around the bonding area of the thermal interface material, and a blocking layer, such as a metal oxide layer, is formed on the surface of the groove to reduce the wetting capability of the thermal interface material, thus further prevents the thermal interface material from wetting the groove in the fusion process performed the thermal interface material, therefore, it ensures the thermal interface material has sufficient thickness for forming solder bonding between the heat sink and the flip chip semiconductor chip.

    Abstract translation: 在本发明中公开了一种散热结构和具有该散热结构的散热半导体封装。 散热半导体封装包括芯片载体，安装并电连接到芯片载体的倒装芯片半导体芯片，以及通过诸如焊料材料的热界面材料接合到倒装芯片半导体芯片的散热器，其中a 在热界面材料的接合区域周围的散热器上形成凹槽，并且在凹槽的表面上形成诸如金属氧化物层的阻挡层，以降低热界面材料的润湿能力，因此进一步 防止热界面材料在进行热界面材料的熔融过程中润湿槽，因此，确保热界面材料具有足够的厚度，用于在散热器和倒装芯片半导体芯片之间形成焊接。

    Apparatus and system for multi-stage event synchronization
    15.
    发明授权
    Apparatus and system for multi-stage event synchronization 失效
    多级事件同步的装置和系统

    公开(公告)号：US06424189B1

    公开(公告)日：2002-07-23

    申请号：US09687418

    申请日：2000-10-13

    Applicant: Jen-Pin Su ,  Tsan-Hui Chen ,  Wen-Hsiang Lin ,  Chun-Chieh Wu ,  Chang-Fu Lin

    Inventor： Jen-Pin Su ,  Tsan-Hui Chen ,  Wen-Hsiang Lin ,  Chun-Chieh Wu ,  Chang-Fu Lin

    IPC: H03L700

    CPC classification number: G06F5/06 ,  H04L7/005 ,  H04L7/02

    Abstract: The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.

    Abstract translation: 本发明公开了一种用于多级事件同步的装置和系统，其主要目的是消除用于平衡在不同频率或时钟相位工作的发起代理和目的代理之间的数据传输的昂贵的同步电路的缺点，如 在现有技术中。 本发明的装置组合了具有多级链的较慢级的链，其中每一级都包括一个简单的同步电路和一个异或门，用于接收从较快级链发送的事件数。 因此，较慢的数据不会错过更快的数据。

    Processing modules with multilevel cache architecture
    17.
    发明授权
    Processing modules with multilevel cache architecture 有权
    处理具有多级缓存架构的模块

    公开(公告)号：US07596661B2

    公开(公告)日：2009-09-29

    申请号：US11307073

    申请日：2006-01-23

    Applicant: Ting-Cheng Hsu ,  Yen-Yu Lin ,  Chih-Wei Ko ,  Chang-Fu Lin

    Inventor： Ting-Cheng Hsu ,  Yen-Yu Lin ,  Chih-Wei Ko ,  Chang-Fu Lin

    IPC: G06F13/00

    CPC classification number: G06F12/0848 ,  G06F12/0857 ,  G06F12/0897

    Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

    Abstract translation: 具有多级缓存架构的处理模块，包括：处理器; 耦合到所述处理器的用于缓存所述处理器的数据的一级（L1）高速缓存，其中所述L1高速缓存具有至少一个L1可高速缓存的范围; 耦合到L1高速缓存用于缓存处理器的数据的二级（L2）高速缓存，其中所述L2高速缓存具有至少一个L2可高速缓存的范围，并且所述L1高速缓存范围和所述L2高速缓存范围是相互排斥的; 以及耦合到L1高速缓存和L2高速缓存的存储器接口，用于在L1高速缓存和存储器之间传送数据并用于在L2高速缓存和存储器之间传送数据。

    GENERAL PURPOSE INTERFACE CONTROLLER OF RESOURE LIMITED SYSTEM
    18.
    发明申请
    GENERAL PURPOSE INTERFACE CONTROLLER OF RESOURE LIMITED SYSTEM 有权
    一般用途接口控制器

    公开(公告)号：US20090182921A1

    公开(公告)日：2009-07-16

    申请号：US12271073

    申请日：2008-11-14

    Applicant: Chang-Fu Lin ,  Shu-Wen Teng ,  Wei Cheng Gu ,  Cheng-Che Chen

    Inventor： Chang-Fu Lin ,  Shu-Wen Teng ,  Wei Cheng Gu ,  Cheng-Che Chen

    IPC: G06F13/00

    CPC classification number: G06F13/387

    Abstract: The invention discloses a general purpose interface controller, including a slave interface controller and a master interface controller, used to exchange data among master devices and slave devices in an electronic device. The slave interface controller receives data and a first control signal from one of the master devices, and converts the first control signal to a request signal. The master interface controller receives the data and the request signal from the slave interface controller, converts the request signal to a second control signal recognized by at least one of the slave devices, and forwards the data and the second control signal to the slave device.

    Abstract translation: 本发明公开了一种通用接口控制器，包括从接口控制器和主接口控制器，用于在电子设备中的主设备和从设备之间交换数据。 从接口控制器从主设备之一接收数据和第一控制信号，并将第一控制信号转换为请求信号。 主接口控制器从从接口控制器接收数据和请求信号，将请求信号转换成由至少一个从设备识别的第二控制信号，并将数据和第二控制信号转发给从设备。

    Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems
    19.
    发明授权
    Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems 有权
    具有指令预取设备的嵌入式系统，以及用于在嵌入式系统中取指令的方法

    公开(公告)号：US07234041B2

    公开(公告)日：2007-06-19

    申请号：US10458470

    申请日：2003-06-10

    Applicant: Chang-Fu Lin

    Inventor： Chang-Fu Lin

    IPC: G06F12/00

    CPC classification number: G06F9/3802 ,  G06F9/3808

    Abstract: In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetch device is also disclosed.

    Abstract translation: 在用于在嵌入式系统中取指令的方法中，当系统总线处于数据访问阶段时，存储在存储器件中的一组指令中的预测的一个指令被取出并随后被存储在指令缓冲器中。 当处理器产生对存储器件的访问请求时，存储在指令缓冲器中的指令中的预测的一个指令被提供给系统总线，以便在确定存储在指令缓冲器中的预测指令之一被命中时被处理器接收 来自处理器的访问请求。 还公开了一种具有指令预取装置的嵌入式系统。

    Semiconductor package with heat sink
    20.
    发明申请
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号：US20050280132A1

    公开(公告)日：2005-12-22

    申请号：US11212290

    申请日：2005-08-26

    Applicant: Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Huang

    Inventor： Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Huang

    IPC: H01L23/367 ,  H01L23/06

    CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/00014

    Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

    Abstract translation: 提供了具有散热器的半导体封装，其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔，允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此，不需要在基板上形成预定的孔，用于连接诸如螺栓的固定构件，并且散热器的结合不会影响迹线布线性以及诸如衬底上的焊球等输入/输出连接的布置 不会导致芯片的裂纹。

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