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公开(公告)号：US10693490B1
公开(公告)日：2020-06-23
申请号：US16529765
申请日：2019-08-01
Applicant: Faraday Technology Corp.
Inventor： Chiao-Min Chen , Min-Yuan Wu , Shih-Yi Shih , Po-Liang Chen
IPC: H03M3/00
Abstract: A Sigma-Delta (Σ-Δ) analog-to-digital converter (ADC) and operation method thereof are provided. The Σ-Δ ADC includes a Σ-Δ modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the Σ-Δ modulator is configured to receive an analog signal. The Σ-Δ modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the Σ-Δ modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the Σ-Δ modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.
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公开(公告)号：US10423188B1
公开(公告)日：2019-09-24
申请号：US16029648
申请日：2018-07-09
Applicant: Faraday Technology Corp.
Inventor： Jin-Sheng Chen
Abstract: In a voltage generating circuit, a bandgap voltage generator has a first operational amplifier to receive a first voltage and a second voltage, and generate a bias voltage by comparing the first voltage and the second voltage, wherein the bandgap voltage generator generates a bandgap current according to the bias voltage and generates an output voltage according to the bandgap current. In a start-up circuit, a comparison circuit compares the first voltage or the second voltage with a reference voltage to generate a first comparison result, and generates a first current according to the first comparison result. A voltage regulator generates a second current according to the first current, and compares the second current with a reference current to generate a second comparison result, and adjusts a voltage value of the bias voltage according to the second comparison result.
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公开(公告)号：US10090853B1
公开(公告)日：2018-10-02
申请号：US15867734
申请日：2018-01-11
Applicant: Faraday Technology Corp.
Inventor： Shu-Dong Wu , Feng Xu
Abstract: An analog-to-digital conversion device is provided for converting an input signal pair to generate an output signal. The analog-to-digital conversion device includes switch groups, capacitors, a comparator, and a controller. The switch groups receive the input signal pair and reference voltages, and selects to output one of the input signal pair and the reference voltages according to a control signal to generate selection voltages respectively. The capacitors receive the selection voltages respectively and generate a first comparison voltage and a second comparison voltage. The comparator compares the first comparison voltage and the second comparison voltage to generate a comparison result signal. The controller sets conversion times for converting bits of the output signal according to the comparison result signal, wherein at least two of the conversion times are different.
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公开(公告)号：US20180034568A1
公开(公告)日：2018-02-01
申请号：US15334297
申请日：2016-10-26
Applicant: Faraday Technology Corp.
Inventor： Chun-Hung Kuo
CPC classification number: H04B17/15 , G01R31/11 , H04B3/46 , H04B17/103
Abstract: A method for performing cable diagnostics in a network system and an associated apparatus are provided, where the network system includes a cable. The method includes: utilizing a transmitter to transmit a zero-crossing signal to a target twisted pair in the cable, wherein the transmitter is positioned in an electronic device within the network system, one end of the cable is electrically connected to the electronic device, and the zero-crossing signal includes a zero-crossing waveform; utilizing a receiver to receive a reflection signal of the zero-crossing signal from the target twisted pair, wherein the receiver is positioned in the electronic device; and detecting at least one characteristic of the reflection signal to generate a determination result, in order to allow the electronic device to process according to the determination result.
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公开(公告)号：US20170097654A1
公开(公告)日：2017-04-06
申请号：US15046425
申请日：2016-02-17
Applicant: Faraday Technology Corp.
Inventor： Chih-Hung Wu
CPC classification number: G06F1/06 , G06F3/0611 , G06F3/0653 , G06F3/0673
Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.
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Patent Agency Ranking
公开(公告)号：US20160363619A1
公开(公告)日：2016-12-15
申请号：US14949888
申请日：2015-11-24
Applicant: Faraday Technology Corp.
Inventor： Pei-Yuan Chou , Jinn-Shyan Wang , Yeong-Jar Chang
CPC classification number: H03K5/14 , G01R31/31709 , G01R31/31937 , H03K2005/00019
Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.
Abstract translation: 用于抖动测量的装置包括第一延迟电路，第二延迟电路和控制电路。 第一延迟电路对输入信号施加初步相位延迟以产生延迟的输入信号。 第二延迟电路与第一延迟电路一起工作，以对延迟的输入信号施加精细相位延迟。 控制电路控制由第一和第二延迟电路施加的延迟量，并且根据由第一和第二延迟电路的延迟元件分别施加的延迟量微调延迟输入信号的相位延迟，并且估计或计算 根据第一和第二延迟电路的调整结果，输入信号的抖动窗口。
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公开(公告)号：US09342087B2
公开(公告)日：2016-05-17
申请号：US14542681
申请日：2014-11-17
Applicant: Faraday Technology Corp.
Inventor： Chi-Yang Chen , San-Yueh Huang
Abstract: A voltage regulator circuit is provided, which includes a main regulator and at least one auxiliary regulator. The main regulator provides an output voltage and regulates the output voltage according to the output voltage and a reference voltage. Each auxiliary regulator is coupled to the main regulator. Each auxiliary regulator also provides the output voltage and regulates the output voltage according to the output voltage and the reference voltage. Each of the main regulator and the at least one auxiliary regulator provides a branch current of the same magnitude. An output current of the voltage regulator circuit includes the branch currents provided by the main regulator and the at least one auxiliary regulator.
Abstract translation: 提供了一种电压调节器电路，其包括主调节器和至少一个辅助调节器。 主调节器提供输出电压，并根据输出电压和参考电压调节输出电压。 每个辅助调节器耦合到主调节器。 每个辅助调节器还提供输出电压，并根据输出电压和参考电压调节输出电压。 主调节器和至少一个辅助调节器中的每一个提供相同幅度的分支电流。 电压调节器电路的输出电流包括由主调节器和至少一个辅助调节器提供的分支电流。
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公开(公告)号：US12244317B2
公开(公告)日：2025-03-04
申请号：US18351513
申请日：2023-07-13
Applicant: Faraday Technology Corp.
Inventor： Vinod Kumar Jain , Mikhail Tamrazyan
Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.
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公开(公告)号：US11909409B1
公开(公告)日：2024-02-20
申请号：US17893191
申请日：2022-08-23
Applicant: Faraday Technology Corp.
Inventor： Vinod Kumar Jain
CPC classification number: H03L7/1976 , H03L7/0891 , H03L7/099
Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.
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公开(公告)号：US11726944B2
公开(公告)日：2023-08-15
申请号：US17542531
申请日：2021-12-06
Applicant: Faraday Technology Corporation , Faraday Technology Corp.
Inventor： Bu-Qing Ping
IPC: G06F13/34 , G06F13/42 , H04L69/324
CPC classification number: G06F13/4221 , H04L69/324 , G06F2213/0026
Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.
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