公开(公告)号：US07355226B2

公开(公告)日：2008-04-08

申请号：US11414308

申请日：2006-05-01

Applicant: Gehan Anil Joseph Amaratunga ,  Florin Udrea

Inventor： Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC: H01L29/786

CPC classification number: H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/78603 ,  H01L29/78624

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.

Abstract translation: 本发明通常涉及诸如功率MOS晶体管，双极晶体管（IGBT），高压二极管等的绝缘栅极等功率半导体及其制造方法。 功率半导体，所述半导体包括功率器件，所述功率器件具有第一和第二电接触区域以及在其间延伸的漂移区域; 以及安装所述装置的半导体衬底; 并且其中所述功率半导体在所述半导体衬底和所述功率器件之间包括电绝缘层，所述电绝缘层具有至少5μm的厚度。

公开(公告)号：US20070200117A1

公开(公告)日：2007-08-30

申请号：US11785276

申请日：2007-04-17

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L31/0312

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

公开(公告)号：US07235439B2

公开(公告)日：2007-06-26

申请号：US11174606

申请日：2005-07-06

Applicant: Florin Udrea ,  Gehan A J Amaratunga

Inventor： Florin Udrea ,  Gehan A J Amaratunga

IPC: H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US07230275B2

公开(公告)日：2007-06-12

申请号：US10984957

申请日：2004-11-10

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/15

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

Abstract translation: 碳化硅半导体器件包括衬底和结场效应晶体管。 晶体管包括：设置在基板上的第一半导体层; 设置在所述第一半导体层的表面上的第一栅极层; 与所述基板上的所述第一栅极层相邻的第一沟道层; 电连接到第一沟道层的第一源极层; 与所述第一沟道层相邻以夹住所述第一沟道层的第二栅极层; 与所述第二栅极层相邻以夹住所述第二栅极层的第二沟道层; 与所述第二沟道层相邻以夹住所述第二沟道层的第三栅极层; 以及电连接到第二沟道层的第二源极层。

公开(公告)号：US20060154401A1

公开(公告)日：2006-07-13

申请号：US11092654

申请日：2005-03-30

Applicant: Julian Gardner ,  James Covington ,  Florin Udrea

Inventor： Julian Gardner ,  James Covington ,  Florin Udrea

IPC: H01L21/00

CPC classification number: G01N27/128

Abstract: A gas-sensing semiconductor device is fabricated on a silicon substrate having a thin silicon oxide insulating layer in which a resistive heater made of a CMOS compatible high temperature metal is embedded. The high temperature metal is tungsten. The device includes at least one sensing area provided with a gas-sensitive layer separated from the heater by an insulating layer. As one of the final fabrication steps, the substrate is back-etched so as to form a thin membrane in the sensing area. Except for the back-etch and the gas-sensitive layer formation, that are carried out post-CMOS, all other layers, including the tungsten resistive heater, are made using a CMOS process employing tungsten metallisation. The device can be monolithically integrated with the drive, control and transducing circuitry using low cost CMOS processing. The heater, the insulating layer and other layers are made within the CMOS sequence and they do not require extra masks or processing.

公开(公告)号：US06858884B2

公开(公告)日：2005-02-22

申请号：US10602065

申请日：2003-06-24

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/868 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/0634 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/861

Abstract: A lateral semiconductor device (10) has a semiconductor layer (15) on an insulating substrate (16). The semiconductor layer (15) has a first region (12) of a first conduction type and a second region (13) of a second conduction type with a drift region (14) therebetween. The drift region (14) is provided by a third region (14″) of the first conduction type and a fourth region (14′) of the second conduction type. The third and fourth (drift) regions (14″,14′) are so arranged that when a reverse voltage bias is applied across the first and second regions (12,13) of the semiconductor layer (15), the third region (14″) has locally in the proximity of the first region (12) an excess of impurity charge relative to the fourth region (14′), and the fourth region (14′) has locally in the proximity of the second region (13) an excess of impurity charge relative to the third region (14″), and the total volume charge in the third region (14″) is substantially equal to the total volume charge in the fourth region (14′).

Abstract translation: 横向半导体器件（10）在绝缘基板（16）上具有半导体层（15）。 半导体层（15）具有第一导电类型的第一区域（12）和第二导电类型的第二区域（13），其间具有漂移区域（14）。 漂移区域（14）由第一导电类型的第三区域（14“）和第二导电类型的第四区域（14'）提供。 第三和第四（漂移）区域（14“，14”）被布置成使得当跨越半导体层（15）的第一和第二区域（12,13）施加反向电压偏压时，第三区域 14“）在第一区域（12）附近具有相对于第四区域（14'）过多的杂质电荷，并且第四区域（14'）局部地位于第二区域（13）附近 ）相对于第三区域（14“）的过量的杂质电荷，并且第三区域（14”）中的总体积电荷基本上等于第四区域（14'）中的总体积电荷。

公开(公告)号：US08928065B2

公开(公告)日：2015-01-06

申请号：US12909033

申请日：2010-10-21

Applicant: Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

Inventor： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC: H01L29/76

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

Abstract translation: 功率晶体管的端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。 掺杂区域具有设置在终端沟槽下方的衬底中的第二类型的导电体。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与边界间隔开的部分MOS栅极的下方延伸到终端沟槽的远侧侧壁。 端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并朝向衬底的边缘延伸。 第一导电层形成在半导体衬底的背面上。 第二导电层形成在有源区顶部，MOS栅极的暴露部分的顶部，并延伸以覆盖端接结构氧化物层的至少一部分。

公开(公告)号：US08859303B2

公开(公告)日：2014-10-14

申请号：US13466626

申请日：2012-05-08

Applicant: Florin Udrea ,  Julian Gardner ,  Syed Zeeshan Ali ,  Mohamed Foysol Chowdhury ,  Ilie Poenaru

Inventor： Florin Udrea ,  Julian Gardner ,  Syed Zeeshan Ali ,  Mohamed Foysol Chowdhury ,  Ilie Poenaru

IPC: H01L21/00 ,  H05B3/26

CPC classification number: H05B3/267 ,  G01J3/108 ,  H05B2203/032

Abstract: An IR source in the form of a micro-hotplate device including a CMOS metal layer made of at least one layer of embedded on a dielectric membrane supported by a silicon substrate. The device is formed in a CMOS process followed by a back etching step. The IR source also can be in the form of an array of small membranes —closely packed as a result of the use of the deep reactive ion etching technique and having better mechanical stability due to the small size of each membrane while maintaining the same total IR emission level. SOI technology can be used to allow high ambient temperature and allow the integration of a temperature sensor, preferably in the form of a diode or a bipolar transistor right below the IR source.

Abstract translation: 微电子装置形式的IR源，其包括由至少一层嵌入在由硅衬底支撑的电介质膜上的CMOS金属层。 该器件以CMOS工艺形成，随后是背蚀刻步骤。 红外光源还可以是小型膜阵列的形式，由于使用了深反应离子蚀刻技术而被密封包装，并且由于每个膜的小尺寸而具有更好的机械稳定性，同时保持相同的总IR 排放水平。 可以使用SOI技术来允许高环境温度并且允许温度传感器的集成，优选地在IR源的正下方的二极管或双极晶体管的形式。

公开(公告)号：US08531857B2

公开(公告)日：2013-09-10

申请号：US12677131

申请日：2008-08-28

Applicant: Akitaka Soeno ,  Jun Saito ,  Gehan Anil Joseph Amaratunga ,  Florin Udrea

Inventor： Akitaka Soeno ,  Jun Saito ,  Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC: H02M7/5387

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H03K17/08128 ,  H03K17/0828

Abstract: In a reverse conducting semiconductor device, which forms a composition circuit, a positive voltage that is higher than a positive voltage of a collector electrode may be applied to an emitter electrode. In this case, in a region of the reverse conducting semiconductor device in which a return diode is formed, a body contact region functions as an anode, a drift contact region functions as a cathode, and current flows from the anode to the cathode. When a voltage having a lower electric potential than the collector electrode is applied to the trench gate electrode at that time, p-type carriers are generated within the cathode and a quantity of carriers increases within the return diode. As a result, a forward voltage drop of the return diode lowers, and constant loss of electric power can be reduced. Electric power loss can be reduced in a power supply device that uses such a composition circuit in which a switching element and the return diode are connected in reverse parallel.

Abstract translation: 在形成合成电路的反向导通半导体器件中，可以将高于集电极的正电压的正电压施加到发射极。 在这种情况下，在形成有返回二极管的反向导通半导体器件的区域中，体接触区域用作阳极，漂移接触区域用作阴极，并且电流从阳极流到阴极。 此时当沟槽栅电极施加具有比集电极电位低的电压的电压时，在阴极内产生p型载流子，在返回二极管内增加载流子数量。 结果，返回二极管的正向压降降低，并且可以减少电力的恒定损失。 在使用其中开关元件和返回二极管反向并联连接的组合电路的电源装置中，电力损耗可以减小。

公开(公告)号：US20130193509A1

公开(公告)日：2013-08-01

申请号：US13131779

申请日：2010-08-10

Applicant: Xiaorong Luo ,  Florin Udrea

Inventor： Xiaorong Luo ,  Florin Udrea

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

Abstract translation: 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。