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20 条记录 (耗时 0.016 秒)

    High-throughput interconnect allowing bus transactions based on partial access requests
    12.
    发明授权
    High-throughput interconnect allowing bus transactions based on partial access requests 失效
    高吞吐量互连允许基于部分访问请求的总线事务

    公开(公告)号：US5911051A

    公开(公告)日：1999-06-08

    申请号：US721686

    申请日：1996-09-27

    申请人： David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case ,  Kim A. Meinerth ,  Brian K. Langendorf

    发明人： David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case ,  Kim A. Meinerth ,  Brian K. Langendorf

    IPC分类号： G06F13/16 ,  G06F13/14

    CPC分类号： G06F13/1631 ,  G06F13/161 ,  G06F13/1615

    摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.

    摘要翻译： 提供了高吞吐量的存储器访问接口。 该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。 每个访问请求包括命令位，地址位和长度位。 在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。 目标设备只需要包含最低位地址位和长度位的段来启动总线事务。 因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。 如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。 访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。

    Wireless video clock synchronization to enable power saving
    15.
    发明授权
    Wireless video clock synchronization to enable power saving 有权
    无线视频时钟同步，实现省电

    公开(公告)号：US08856842B2

    公开(公告)日：2014-10-07

    申请号：US13706685

    申请日：2012-12-06

    申请人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

    发明人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

    IPC分类号： H04N7/18 ,  H04N21/43 ,  H04N21/4363 ,  H04N21/41

    CPC分类号： H04N21/43637 ,  H04N21/4104 ,  H04N21/4305

    摘要： In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.

    摘要翻译： 在无线视频系统中，用于从发送装置无线发送视频数据的时钟速率应与用于在接收装置处接收视频数据的时钟速率相同。 但是这两个设备具有单独的时钟，其频率可能会随着时间的推移而分离，导致视频缓冲区运行或运行不足。 当首次获取时钟同步并且在已经实现时钟同步并且仅仅被维持之后的较大间隔时，可以以短时间间隔发送用于防止这种情况的时钟同步消息。

    WIRELESS VIDEO CLOCK SYNCHRONIZATION TO ENABLE POWER SAVING
    17.
    发明申请
    WIRELESS VIDEO CLOCK SYNCHRONIZATION TO ENABLE POWER SAVING 有权
    无线视频时钟同步使能节电

    公开(公告)号：US20130179929A1

    公开(公告)日：2013-07-11

    申请号：US13706685

    申请日：2012-12-06

    申请人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

    发明人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

    IPC分类号： H04N21/4363

    CPC分类号： H04N21/43637 ,  H04N21/4104 ,  H04N21/4305

    摘要： In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.

    摘要翻译： 在无线视频系统中，用于从发送装置无线发送视频数据的时钟速率应与用于在接收装置处接收视频数据的时钟速率相同。 但是这两个设备具有单独的时钟，其频率可能会随着时间的推移而分离，导致视频缓冲区运行或运行不足。 当首次获取时钟同步并且在已经实现时钟同步并且仅仅被维持之后的较大间隔时，可以以短时间间隔发送用于防止这种情况的时钟同步消息。

    System and method for placement of operands in system memory
    18.
    发明授权
    System and method for placement of operands in system memory 失效
    在系统内存中放置操作数的系统和方法

    公开(公告)号：US6097402A

    公开(公告)日：2000-08-01

    申请号：US21192

    申请日：1998-02-10

    申请人： Colyn Case ,  Brian K. Langendorf ,  George R. Hayek ,  Kim A. Meinerth

    发明人： Colyn Case ,  Brian K. Langendorf ,  George R. Hayek ,  Kim A. Meinerth

    IPC分类号： G06F3/14 ,  G06F15/167

    CPC分类号： G06F3/14

    摘要： A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.

    摘要翻译： 一种用于通过在主存储器中选择放置至少一个图形操作数来增强图形处理的方法和系统。 该系统包括通过诸如加速图形端口（AGP）总线的专用图形总线与系统存储器通信的图形控制器。 这允许纹理贴图，alpha混合数据和其他图形信息包含在系统存储器中，而不会降低系统性能。

    Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
    19.
    发明授权
    Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge 失效
    仲裁信令机制，以防止死锁保证访问延迟，并保证扩展桥的采集延迟

    公开(公告)号：US5625779A

    公开(公告)日：1997-04-29

    申请号：US366964

    申请日：1994-12-30

    申请人： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

    发明人： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

    IPC分类号： G06F13/364 ,  G06F13/40 ,  G06F13/36

    CPC分类号： G06F13/364 ,  G06F13/4031 ,  G06F13/4036

    摘要： An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

    摘要翻译： 耦合在扩展桥和主桥之间的中间总线的仲裁信令机制，用于管理通过中间总线的通信。 主桥包括用于在CPU和扩展桥之间发布事务的CPU发布缓冲器，以及用于存储要写入到DRAM中的数据的DRAM缓冲器。 主桥还包括耦合以从扩展桥接器和耦合到扩展桥的任何其它总线代理接收请求信号的仲裁器。 响应于扩展桥的请求，仲裁器在确认确认信号之前清空CPU发布缓冲区和DRAM缓冲区。 提供了一种被动释放方法，其包括在扩展桥具有总线控制的通信周期期间通过扩展桥信令发送被动释放语义。 主桥可以在再次允许进入扩建桥之前，暂时使用公交车给另一个总线代理。

    Method and apparatus for latching data from a memory resource at a datapath unit
    20.
    发明授权
    Method and apparatus for latching data from a memory resource at a datapath unit 失效
    用于在数据路径单元处从存储器资源锁存数据的方法和装置

    公开(公告)号：US06112284A

    公开(公告)日：2000-08-29

    申请号：US367807

    申请日：1994-12-30

    申请人： George R. Hayek ,  Joe M. Nardone ,  Aniruddha Kundu ,  Kuljit S. Bains

    发明人： George R. Hayek ,  Joe M. Nardone ,  Aniruddha Kundu ,  Kuljit S. Bains

    IPC分类号： G11C7/10 ,  G06F13/16

    CPC分类号： G11C7/1018 ,  G11C7/1024

    摘要： A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.

    摘要翻译： 具有在具有扩展数据输出（EDO）DRAM的计算机系统中跟踪列存取选通信号的数据选通器的存储器控​​制器。 数据选通信号以预定的延迟跟随列存取选通信号，因此列存取选通信号中的任何偏移固有地包括在数据选通信号内。 结果，可以在有效窗口的大约中心处响应于所述数据选通信号来锁存数据。