公开(公告)号：US20120199915A1

公开(公告)日：2012-08-09

申请号：US13446462

申请日：2012-04-13

Applicant: Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

Inventor： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC: H01L27/105

CPC classification number: H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

Abstract translation: 本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US20110170335A1

公开(公告)日：2011-07-14

申请号：US13071882

申请日：2011-03-25

Applicant: Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

Inventor： Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

IPC: G11C11/34

CPC classification number: H01L27/101 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C2213/79 ,  H01L29/8618

Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.

Abstract translation: 提供一种用于访问非易失性存储单元的半导体器件。 在一些实施例中，半导体器件具有包括源极，漏极和阱的半导体层的垂直堆叠。 向半导体器件施加漏极 - 源极偏置电压在阱上产生穿透机构以引发源极和漏极之间的电流。

公开(公告)号：US20110093954A1

公开(公告)日：2011-04-21

申请号：US12638690

申请日：2009-12-15

Applicant: Hyung Kyu LEE ,  Jong-Wook HAN ,  Hyun sook CHO

Inventor： Hyung Kyu LEE ,  Jong-Wook HAN ,  Hyun sook CHO

IPC: G06F11/00

CPC classification number: H04L63/1433 ,  G06F21/577

Abstract: An apparatus for remotely diagnosing security vulnerabilities, includes a vulnerability analysis unit for obtaining service information by searching a target device of a specific network and a port of the target device, searching a profile DB for principal characteristic information of the acquired service information, determining a query key type based on the retrieved principal characteristic information to acquire a vulnerability diagnosis list present in the principal characteristic information from a vulnerability list management DB; and an attack agent for diagnosing a vulnerability of the principal characteristic information on the vulnerability diagnosis list based on preset characteristic information. Further, the apparatus includes a result analysis unit for reporting a result of the diagnosis of the vulnerability of the principal characteristic information; and a GUI management unit for performing interfacing of the result of the diagnosis of the vulnerability of the principal characteristic information to a vulnerability diagnosis tool.

Abstract translation: 一种用于远程诊断安全漏洞的装置，包括：通过搜索特定网络的目标设备和目标设备的端口来获取服务信息的漏洞分析单元，在简档DB中搜索所获取的服务信息的主要特性信息，确定 基于检索到的主要特征信息的查询密钥类型，以从脆弱性列表管理DB获取存在于主要特征信息中的漏洞诊断列表; 以及基于预设特征信息来诊断脆弱性诊断列表上的主要特征信息的脆弱性的攻击代理。 此外，该装置包括：结果分析单元，用于报告主要特征信息的脆弱性的诊断结果; 以及GUI管理单元，用于执行将主要特征信息的脆弱性的诊断结果与脆弱性诊断工具的接口。

公开(公告)号：US20100228976A1

公开(公告)日：2010-09-09

申请号：US12619150

申请日：2009-11-16

Applicant: Hyung Kyu LEE ,  Geon Woo KIM ,  Seung-Hee OH ,  Chol Soon JANG ,  Jong-Wook HAN

Inventor： Hyung Kyu LEE ,  Geon Woo KIM ,  Seung-Hee OH ,  Chol Soon JANG ,  Jong-Wook HAN

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/00

CPC classification number: H04L9/083 ,  H04L9/0838 ,  H04L9/3271 ,  H04L63/062 ,  H04L2209/60

Abstract: At least one client robot in a domain are connected to a domain security management unit and a root security management unit is connected to at least one external server outside the domain and the domain security management unit via a network. A method for providing secured network robot services includes generating, at the domain security management unit, a shared key between the client robot and the external server when the client robot requests key distribution; generating, at the domain security management unit, a key distribution request message containing the shared key; and transmitting, at the domain security management unit, the key distribution request message to the external server.

Abstract translation: 域中的至少一个客户端机器人连接到域安全管理单元，并且根安全管理单元经由网络连接到域外的至少一个外部服务器和域安全管理单元。 一种用于提供安全的网络机器人服务的方法，包括：当客户端机器人请求密钥分发时，在域安全管理单元处生成客户机器人与外部服务器之间的共享密钥; 在所述域安全管理单元处生成包含所述共享密钥的密钥分发请求消息; 以及在所述域安全管理单元处向所述外部服务器发送所述密钥分发请求消息。

公开(公告)号：US20100141094A1

公开(公告)日：2010-06-10

申请号：US12501158

申请日：2009-07-10

Applicant: Hyung-Kyu Lee ,  Michael Xuefei Tang

Inventor： Hyung-Kyu Lee ,  Michael Xuefei Tang

IPC: H02N2/18 ,  F03G7/08

CPC classification number: H02N2/186 ,  F03G7/08

Abstract: A mechanical energy harvester, such as for an electronic system such as a sensor system. The energy harvester has a spring with one end connected to a support structure, and a piezoelectric material on the spring. An electronics package is supported on the spring, the electronics package comprising at least one component selected from the group consisting of rectifier(s), storage component(s), and integrated circuit(s).

Abstract translation: 机械能量收集器，例如用于诸如传感器系统的电子系统。 能量收集器具有弹簧，其一端连接到支撑结构，弹簧上具有压电材料。 电子封装支撑在弹簧上，电子封装包括从由整流器，存储部件和集成电路组成的组中选择的至少一个部件。

公开(公告)号：US20120080725A1

公开(公告)日：2012-04-05

申请号：US12894405

申请日：2010-09-30

Applicant: Peter Nicholas Manos ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir ,  Brian Lee ,  Dadi Setiadi

Inventor： Peter Nicholas Manos ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir ,  Brian Lee ,  Dadi Setiadi

IPC: H01L27/08 ,  H01L21/02

CPC classification number: H01L27/101 ,  G11C11/16 ,  H01L21/823487 ,  H01L27/228 ,  H01L27/2454 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.

Abstract translation: 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 导电互连元件沉积在至少选定的垂直柱晶体管上，并且非挥发性可变电阻存储单元沉积在导电互连层上以形成垂直晶体管存储器阵列。

公开(公告)号：US08045361B2

公开(公告)日：2011-10-25

申请号：US12501140

申请日：2009-07-10

Applicant: Hyung-Kyu Lee ,  YoungPil Kim ,  Chulmin Jung

Inventor： Hyung-Kyu Lee ,  YoungPil Kim ,  Chulmin Jung

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2213/79

Abstract: A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.

Abstract translation: 非易失性存储单元和向其写入数据的方法。 根据一些实施例，存储器单元包括被配置为同时存储互补的编程电阻状态的第一和第二电阻性存储元件（RME）。 第一RME被编程为第一电阻状态，并且通过在所选择的方向上通过存储器单元施加公共写入电流，将第二RME同时编程为第二电阻状态。

公开(公告)号：US20110007597A1

公开(公告)日：2011-01-13

申请号：US12502219

申请日：2009-07-13

Applicant: Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

Inventor： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.

Abstract translation: 用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。 根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。 耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压 并且向剩余的2N-1个输出线同时施加第二电压。

公开(公告)号：US08208285B2

公开(公告)日：2012-06-26

申请号：US12502089

申请日：2009-07-13

Applicant: Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

Inventor： Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C7/00 ,  G11C7/22 ,  G11C7/12 ,  G11C11/16

CPC classification number: H01L27/101 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C2213/79 ,  H01L29/8618

Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.

Abstract translation: 提供一种用于访问非易失性存储单元的半导体器件。 在一些实施例中，半导体器件具有包括源极，漏极和阱的半导体层的垂直堆叠。 向半导体器件施加漏极 - 源极偏置电压在阱上产生穿透机构以引发源极和漏极之间的电流。

公开(公告)号：US20120150363A1

公开(公告)日：2012-06-14

申请号：US13309763

申请日：2011-12-02

Applicant: Hyung Kyu LEE ,  Byung-Gil LEE

Inventor： Hyung Kyu LEE ,  Byung-Gil LEE

IPC: G08G3/00

CPC classification number: G08G3/00

Abstract: An apparatus for vessel traffic management mounted in a vessel creates vessel sailing information including a current location and an identifier of the vessel in accordance with a navigation plan to a destination of the vessel; calculates an estimated time for arriving at the destination based on a distance between the current location and the destination and a sailing speed; and calculates an estimated entry time of entering a target area within the destination based on a distance between the current location and the destination and the sailing speed. The vessel sailing information, the estimated arrival time, and the estimated entry time are transmitted to a local control center, and the sailing of the vessel is controlled using a vessel traffic condition at the target area, provided from the local control center.

Abstract translation: 装在船上的船舶交通管理装置根据导航计划向船只的目的地建立船舶航行信息，包括当前位置和船只的标识符; 基于当前位置和目的地之间的距离和航行速度来计算到达目的地的估计时间; 并且基于当前位置和目的地之间的距离以及航行速度来计算进入目的地内的目标区域的估计进入时间。 船舶航行信息，预计到达时间和估计的进入时间被传送到本地控制中心，并且使用从当地控制中心提供的目标区域的船舶交通状况来控制船舶的航行。