公开(公告)号：US10256180B2

公开(公告)日：2019-04-09

申请号：US15461499

申请日：2017-03-17

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/29 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

公开(公告)号：US10090256B2

公开(公告)日：2018-10-02

申请号：US15364185

申请日：2016-11-29

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H05K1/03 ,  H05K3/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

Abstract: A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.

公开(公告)号：US20170194241A1

公开(公告)日：2017-07-06

申请号：US15461499

申请日：2017-03-17

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

公开(公告)号：US20170077045A1

公开(公告)日：2017-03-16

申请号：US15364185

申请日：2016-11-29

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/35121 ,  H05K1/0373 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014

Abstract: A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.

Abstract translation: 半导体结构包括绝缘层，多个阶梯形导电通孔和图案化电路层。 绝缘层包括顶表面和与顶表面相对的底表面。 阶梯状导电通孔设置在绝缘层处以电连接顶表面和底表面。 每个阶梯式导电通孔包括头部和连接到头部的颈部。 头部设置在顶表面上，头部的上表面与顶表面共面。 头部的最小直径大于颈部的最大直径。 图案化电路层设置在顶表面上并电连接到阶梯式导电通孔。

公开(公告)号：US09859193B2

公开(公告)日：2018-01-02

申请号：US15600793

申请日：2017-05-22

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/495 ,  H01L23/60

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/053 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/60 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.

公开(公告)号：US09801282B2

公开(公告)日：2017-10-24

申请号：US15232808

申请日：2016-08-10

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H05K7/10 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K1/02 ,  H05K3/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

CPC classification number: H05K1/181 ,  H05K1/0218 ,  H05K1/0353 ,  H05K1/0373 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure includes a substrate, a sensor, a base, a lead frame, conductive vias and patterned circuit layer. The substrate includes a component-disposing region and electrode contacts. The sensor is disposed at the component-disposing region and electrically connected to the electrode contacts. The base covers the substrate with its bonding surface and includes a receiving cavity, a slanted surface extended between a bottom surface of the receiving cavity and the bonding surface, and electrodes disposed on the bonding surface and electrically connected to the electrode contacts respectively. The sensor is located in the receiving cavity. The lead frame is disposed at the base. The conductive vias penetrates the base and electrically connected to the lead frame. The patterned circuit layer is disposed on the slanted surface and electrically connected to the conductive vias and the electrodes.

公开(公告)号：US20160353575A1

公开(公告)日：2016-12-01

申请号：US15232808

申请日：2016-08-10

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H05K1/18 ,  H05K1/03 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K1/0218 ,  H05K1/0353 ,  H05K1/0373 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure includes a substrate, a sensor, a base, a lead frame, conductive vias and patterned circuit layer. The substrate includes a component-disposing region and electrode contacts. The sensor is disposed at the component-disposing region and electrically connected to the electrode contacts. The base covers the substrate with its bonding surface and includes a receiving cavity, a slanted surface extended between a bottom surface of the receiving cavity and the bonding surface, and electrodes disposed on the bonding surface and electrically connected to the electrode contacts respectively. The sensor is located in the receiving cavity. The lead frame is disposed at the base. The conductive vias penetrates the base and electrically connected to the lead frame. The patterned circuit layer is disposed on the slanted surface and electrically connected to the conductive vias and the electrodes.

Abstract translation: 封装结构包括基板，传感器，基座，引线框架，导电通孔和图案化电路层。 基板包括部件布置区域和电极触点。 传感器设置在部件布置区域处并电连接到电极触点。 基座覆盖基板与其接合表面，并且包括接收腔，在接收腔的底表面和接合表面之间延伸的倾斜表面，以及设置在接合表面上并电连接到电极触头的电极。 传感器位于接收腔中。 引线框架设置在基座上。 导电通孔穿透基座并电连接到引线框架。 图案化电路层设置在倾斜表面上并电连接到导电通孔和电极。

公开(公告)号：US20160034083A1

公开(公告)日：2016-02-04

申请号：US14581835

申请日：2014-12-23

Applicant: IBIS INNOTECH INC.

Inventor： Wei-Jen LAI ,  Chih-Kung HUANG

IPC: G06F3/041

CPC classification number: G06F3/044 ,  G06F3/041 ,  G06F2203/04103

Abstract: A touch sensing device includes a light-transmitting substrate, an edge layer and sensing lines. The light-transmitting substrate has an upper surface and a lower surface opposite to the upper surface, and the edge layer is covered on an edge of the upper surface of the light-transmitting substrate. The edge layer has a main body made of insulated material, and conductive wires. The main body has a first surface attached on the upper surface of the light-transmitting substrate, a second surface opposite and parallel to the first surface, and slots recessed downwardly from the second surface. The conductive wires are embedded in the slots, respectively. The sensing lines are disposed on the upper surface of the light-transmitting substrate and electrically connected with the conductive wires, respectively. Therefore, the touch sensing device can have simple and quick manufacturing process, high yield rate and low cost.

Abstract translation: 触摸感测装置包括透光衬底，边缘层和感测线。 透光基板具有与上表面相对的上表面和下表面，并且边缘层被覆盖在透光基板的上表面的边缘上。 边缘层具有由绝缘材料制成的主体和导电线。 主体具有附着在透光基板的上表面上的第一表面，与第一表面相对并平行的第二表面，以及从第二表面向下凹陷的槽。 导线分别嵌入槽中。 感测线设置在透光基板的上表面上并分别与导电线电连接。 因此，触摸传感装置可以具有简单快速的制造工艺，高产率和低成本。