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公开(公告)号：US06369397B1
公开(公告)日：2002-04-09
申请号：US09225120
申请日：1999-01-04
IPC分类号： G01N1310
CPC分类号： H01J37/3045 , H01J37/3174 , H01J2237/3175 , Y10S977/85
摘要： A method and apparatus for positioning a wafer in an electron beam lithography system. This method includes the steps of positioning a scanned probe microscope in the lithography system, and determining the distance between a preset location on the scanned probe microscope and a reference position in the lithography system. The wafer is brought into physical contact with that preset location, and then the wafer is moved a predetermined distance from the preset location on order to position the wafer at the desired focal plane in the lithography system.
摘要翻译： 一种用于在电子束光刻系统中定位晶片的方法和装置。 该方法包括以下步骤：将扫描的探针显微镜放置在光刻系统中，以及确定扫描的探针显微镜上的预设位置与光刻系统中的参考位置之间的距离。 将晶片与该预设位置物理接触，然后将晶片从预置位置移动预定距离，以将晶片定位在光刻系统中所需的焦平面处。
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12.发明申请公开(公告)号：US20120127442A1
公开(公告)日：2012-05-24
申请号：US12953511
申请日：2010-11-24
IPC分类号： G03B27/42
摘要： The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.
摘要翻译： 本文公开的主题涉及使用光学邻近校正验证的模拟来确定光刻设置点。 在一个实施例中，公开了一种用于确定光刻工艺的光刻工具设定点的计算机实现的方法。 该方法可以包括：提供生产平版印刷工艺的模型，包括印刷形状的模拟; 分析生产光刻工艺的模型，以确定在生产光刻工艺中用于产生印刷形状的生产掩模上的一组结构是否将在多个设定点下失效; 确定生产掩模上的一组结构不失败的设定点的操作区域; 以及基于设定点选择功能在操作区域内建立设定点位置。
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公开(公告)号：US20110061030A1
公开(公告)日：2011-03-10
申请号：US12555219
申请日：2009-09-08
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.
摘要翻译： 公开了用于验证光掩模设计的解决方案。 在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。
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公开(公告)号：US07257247B2
公开(公告)日：2007-08-14
申请号：US09683836
申请日：2002-02-21
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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公开(公告)号：US06577406B2
公开(公告)日：2003-06-10
申请号：US09683551
申请日：2002-01-17
申请人： James A. Bruce , Orest Bula , Emily E. Fisch
发明人： James A. Bruce , Orest Bula , Emily E. Fisch
IPC分类号： G01B1100
CPC分类号： G03F7/70641
摘要： A control target structure and method for monitoring the lithographic affects on minimum feature in a lithographic process. The control target uses line array elements having a nominal width. By changing the shape of the line-ends of the elements the control target can be optimized for controlling either focus or dose.
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公开(公告)号：US06300228B1
公开(公告)日：2001-10-09
申请号：US09386089
申请日：1999-08-30
申请人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
发明人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
IPC分类号： H01L2122
CPC分类号： H01L21/268 , H01L21/0455 , H01L21/2255
摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.
摘要翻译： 用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。 通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。 然后将衬底（30）退火。 退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。 退火过程也使非晶区域（32）半导体材料结晶。 基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。 掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。
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公开(公告)号：US5614990A
公开(公告)日：1997-03-25
申请号：US298643
申请日：1994-08-31
申请人： James A. Bruce , Joseph Gortych , Michael S. Hibbs
发明人： James A. Bruce , Joseph Gortych , Michael S. Hibbs
IPC分类号： G02B5/23 , G03C1/725 , G03F7/20 , H01L21/027 , G03B27/42
CPC分类号： G02F1/0126 , G03F7/70058 , G02F2203/52
摘要： Photochromic glass is situated between a light source for exposing resist coated on a wafer and the wafer. The photochromic glass is activated by a wavelength different from that which activates the resist. An array of individual light sources, each of varying intensity, provide activation light to the photochromic glass. A CCD array temporarily in the imaging plane measures light intensity distribution. A controller varies the individual light source array intensities to activate the photochromic glass to varying degrees to produce a desired effect at the imaging plane.
摘要翻译： 光致变色玻璃位于用于曝光涂覆在晶片上的抗蚀剂的光源和晶片之间。 光致变色玻璃由与激活抗蚀剂的波长不同的波长激活。 每个具有不同强度的单个光源的阵列向光致变色玻璃提供活化光。 成像平面中暂时的CCD阵列测量光强分布。 控制器改变各个光源阵列强度，以使光致变色玻璃以不同程度激活，以在成像平面产生期望的效果。
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公开(公告)号：US4612805A
公开(公告)日：1986-09-23
申请号：US685867
申请日：1984-12-24
IPC分类号： G01R31/26 , G01N3/00 , G01N19/04 , G01N33/38 , H01L21/66 , H01L23/544 , G01B21/08 , G01N3/08
CPC分类号： H01L22/34 , G01N19/04 , G01N2203/0091 , G01N33/388
摘要： A test site for gauging the adhesion between the insulating layers and the metal layers used to produce the various devices on a semiconductor chip. The chip-sized test site can be formed along with the product chips on the product wafers. The layers of the test site are arranged such that a first polyimide layer forms a first test interface with a silicon nitride layer and a second test interface with a first metal layer, and a second polyimide layer forms a third test interface with a second metal layer, a fourth test interface with the first polyimide layer, and a fifth test interface with the silicon nitride layer. These five interfaces form a single continuous adhesion test interface. During a 90.degree. peel test, the layers of the test site will sequentially separate along this interface. Thus, the adhesion at five different interfaces can be tested during a single peel test on a chip-sized test site.
摘要翻译： 用于测量绝缘层和用于在半导体芯片上制造各种器件的金属层之间的粘合性的测试部位。 芯片尺寸的测试点可以与产品晶片上的产品芯片一起形成。 测试部位的层被布置成使得第一聚酰亚胺层与氮化硅层形成第一测试界面和与第一金属层形成第二测试界面，并且第二聚酰亚胺层与第二金属层形成第三测试界面 与第一聚酰亚胺层的第四测试界面，以及与氮化硅层的第五测试界面。 这五个界面形成一个单一的连续粘附测试界面。 在90°剥离试验中，试验部位的层将沿着该界面顺序分离。 因此，在芯片尺寸的测试部位的单次剥离测试期间，可以测试五个不同界面处的粘附。
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19.发明申请公开(公告)号：US20120192124A1
公开(公告)日：2012-07-26
申请号：US13014159
申请日：2011-01-26
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.
摘要翻译： 公开了在光学邻近校正验证期间在光刻工艺中考虑光掩模偏差的解决方案。 在一个实施例中，一种方法包括：识别表示第一芯片或切口之一的数据集中的晶片控制结构; 在晶片控制结构处于表示第一芯片的数据集的情况下，偏置表示第一芯片的数据组; 在晶片控制结构处于表示切口或第二芯片的数据组的情况下，偏置表示切口的数据组或不同于第一芯片的第二芯片; 模拟晶圆控制结构的形成; 确定模拟晶片控制结构是否符合目标控制结构; 并且在模拟晶片控制结构不符合目标控制结构的情况下，迭代地调整曝光剂量条件。
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公开(公告)号：US07492941B2
公开(公告)日：2009-02-17
申请号：US11769431
申请日：2007-06-27
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
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