公开(公告)号：US20050074558A1

公开(公告)日：2005-04-07

申请号：US10863113

申请日：2004-06-07

Applicant: Hong-Je Cho ,  Jin-Su Kim ,  Sung-Chul Kang

Inventor： Hong-Je Cho ,  Jin-Su Kim ,  Sung-Chul Kang

IPC: G02F1/13 ,  B05B1/20 ,  B05B9/00 ,  B05B12/10 ,  B05C5/00 ,  B05C11/10 ,  G02F1/1333 ,  H01L21/00

CPC classification number: B05B1/205 ,  B05C11/1007 ,  B05C11/1042 ,  H01L21/6708

Abstract: A process solution supply system and method for advantageously supplying process solution are provided. A process solution supply device provides process solution at a controlled temperature to a processing unit for injection of the process solution onto substrates through a plurality of nozzles. The process solution is transported to the nozzles through a pathway, which in one example can include a piping arrangement. The pathway advantageously uses temperature control through contact piping, a thermo-sensor, and piping arrangement, such that the process solution injected through the plurality of nozzles is substantially equal to the temperature of the process solution originally supplied from the process solution supply device.

Abstract translation: 提供了一种用于有利地提供处理方案的工艺解决方案供应系统和方法。 处理溶液供应装置将处理溶液以受控的温度提供给处理单元，用于通过多个喷嘴将工艺溶液注入到基材上。 工艺溶液通过一个通道输送到喷嘴，在一个示例中可以包括管道装置。 该通道有利地通过接触管道，热传感器和管道布置来进行温度控制，使得通过多个喷嘴注入的处理溶液基本上等于从过程溶液供应装置最初提供的处理溶液的温度。

公开(公告)号：US6124149A

公开(公告)日：2000-09-26

申请号：US184514

申请日：1998-11-02

Applicant: Kyung Wook Paik ,  Jin Su Kim ,  Hyung Su Ko

Inventor： Kyung Wook Paik ,  Jin Su Kim ,  Hyung Su Ko

IPC: H01L21/301 ,  H01L21/822 ,  H01L21/98 ,  H01L25/065 ,  H01L27/00 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/0002

Abstract: A stackable semiconductor chip package, methods of fabricating the chip package, and a stacked semiconductor chip module are disclosed. In the chip package or the chip module, lateral surfaces of each semiconductor chip are insulated with insulation regions that are formed while the chip is still part of an uncut wafer. The fabrication methods include the steps of: preparing an uncut wafer having multiple chip portions; forming slots along a pair of opposed lateral sides of the chip portions; filling the slots with an insulating material; forming a first insulation layer on an upper surface of the wafer; forming via holes in the first insulation layer so that chip pads formed in each chip portion are exposed through the via holes; forming a plurality of conductive patterns on the first insulation layer so that the conductive patterns are electrically coupled to the chip pads through the via holes; forming a second insulation layer on the conductive patterns and the first insulation layer; and cutting the wafer along the cutting lines. In alternate methods, two or more wafers may be stacked before the cutting step is performed. This results in the formation of multiple stacked chip modules.

Abstract translation: 公开了可堆叠的半导体芯片封装，制造芯片封装的方法和堆叠的半导体芯片模块。 在芯片封装或芯片模块中，每个半导体芯片的侧表面被绝缘，当芯片仍然是未切割晶片的一部分时形成的绝缘区域。 制造方法包括以下步骤：制备具有多个芯片部分的未切割晶片; 沿所述芯片部分的一对相对的侧面形成槽; 用绝缘材料填充槽; 在所述晶片的上表面上形成第一绝缘层; 在所述第一绝缘层中形成通孔，使得形成在每个芯片部分中的芯片焊盘通过所述通孔露出; 在所述第一绝缘层上形成多个导电图案，使得所述导电图案通过所述通孔与所述芯片焊盘电耦合; 在所述导电图案和所述第一绝缘层上形成第二绝缘层; 并沿切割线切割晶片。 在替代方法中，在执行切割步骤之前可以堆叠两个或更多个晶片。 这导致形成多个堆叠的芯片模块。

公开(公告)号：US09491866B2

公开(公告)日：2016-11-08

申请号：US13809083

申请日：2011-07-07

Applicant: Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

Inventor： Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/00 ,  H05K3/02 ,  H05K3/46 ,  H05K3/04

CPC classification number: H05K3/062 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/02 ,  H05K3/045 ,  H05K3/108 ,  H05K3/465 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49167

Abstract: Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without perfolining a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.

Abstract translation: 提供一种印刷电路板的制造方法。 制造印刷电路板的方法包括制备绝缘板，将激光照射到灰蒙蒙掩模到绝缘板的每个表面上，从而同时形成电路图案槽和通孔，并填充电路图案 沟槽和通孔形成掩埋电路图案和通孔。 因此，电路图案槽和通孔可以同时使用灰蒙版掩模形成，而不需要单独的用于形成通孔的工艺。 因此，可以简化制造过程以降低制造成本。

公开(公告)号：US09488764B2

公开(公告)日：2016-11-08

申请号：US13240028

申请日：2011-09-22

Applicant: Young-Jae Lee ,  Jin Su Kim ,  Jun Lee

Inventor： Young-Jae Lee ,  Jin Su Kim ,  Jun Lee

IPC: G02B5/30

CPC classification number: G02B5/3058

Abstract: Provided are a wire grid polarizer and a backlight unit using the wire grid polarizer. The wire grid polarizer comprises a first grid layer formed on a substrate and provided with at least one of a first grid pattern, and a second grid layer formed on the first grid pattern and provided with at least one of a second grid pattern made of metal material wherein the first grid layer is made of high molecular substance having a lower refraction index than that of the substrate. By forming a first grid pattern on a substrate using a high molecular substance layer and by forming a metal grid pattern on the first grid pattern, transmission rates of respective wavelengths depending on light angles of incident light are controlled and thereby minimize color variations depending on view angle.

Abstract translation: 提供了使用线栅偏振器的线栅偏振器和背光单元。 线栅偏振器包括形成在基板上的第一栅格层，并且设置有形成在第一栅格图案上的第一栅格图案和第二栅格层中的至少一个，并且设置有由金属制成的第二栅格图案中的至少一个 材料，其中第一栅格层由具有比衬底的折射率低的折射率的高分子物质制成。 通过使用高分子物质层在基板上形成第一栅格图案，并且通过在第一栅格图案上形成金属栅格图案，控制取决于入射光的光角的各波长的透射率，从而根据视图最小化颜色变化 角度。

公开(公告)号：US09265161B2

公开(公告)日：2016-02-16

申请号：US12956545

申请日：2010-11-30

Applicant: Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

Inventor： Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/46 ,  H05K3/18 ,  H05K3/00 ,  H05K3/04

CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/184 ,  H05K3/4661 ,  H05K2203/054 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.

Abstract translation: 提供嵌入式PCB，使用嵌入式PCB的多层PCB及其制造方法。 制造嵌入式PCB的方法包括：使用激光使绝缘层图案化的第一步骤，使得绝缘层的一部分被选择性地蚀刻以形成电路图案区域;以及第二步骤， 图案区域与电镀材料形成电路图案。 因此，制造嵌入式PCB的方法可以使用激光器同时或顺序地蚀刻光致抗蚀剂层和绝缘层，以形成电路图案，从而获得微图案并简化制造工艺，并实现多层结构的对准精度 使用嵌入式PCB的PCB层，从而提高产品的可靠性和产量。

公开(公告)号：US09158052B2

公开(公告)日：2015-10-13

申请号：US13242802

申请日：2011-09-23

Applicant: Jin Su Kim ,  Kyoung Jong Yoo ,  Young-Jae Lee ,  Jun Lee

Inventor： Jin Su Kim ,  Kyoung Jong Yoo ,  Young-Jae Lee ,  Jun Lee

IPC: H01B13/00 ,  G02B5/30 ,  G03F7/20

CPC classification number: G02B5/3058 ,  G03F7/20

Abstract: Provided is a method of manufacturing a wire grid polarizer in which a stable color coordinate can be implemented. According to the present invention, in a process where a second grid pattern of metal pattern is formed over a first grid pattern made of resin material, metal layer is deposited in a concave portion formed between adjacent first grid patterns to form void portion and a width and a height of the second grid pattern are adjusted depending on adjustment of a width of the voids, and thereby improving a process efficiency.

Abstract translation: 提供一种可以实现稳定的色坐标的线栅偏振器的制造方法。 根据本发明，在由树脂材料制成的第一格栅图案上形成金属图案的第二格栅图案的方法中，金属层沉积在形成在相邻的第一格栅图案之间的凹部中，形成空隙部分和宽度 并且根据空隙的宽度的调整来调整第二格栅图案的高度，从而提高处理效率。

公开(公告)号：US08821740B2

公开(公告)日：2014-09-02

申请号：US14130146

申请日：2012-06-28

Applicant: Young Jae Lee ,  Kyoung Jong Yoo ,  Jun Lee ,  Jin Su Kim ,  Jae Wan Park

Inventor： Young Jae Lee ,  Kyoung Jong Yoo ,  Jun Lee ,  Jin Su Kim ,  Jae Wan Park

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC classification number: C23C14/0005 ,  B22F1/0044 ,  B22F9/16 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C04B35/622 ,  C23C16/01 ,  C30B11/12 ,  C30B29/60 ,  H01L29/0673 ,  H01L29/66469 ,  H01L29/775 ,  Y10S977/888 ,  Y10S977/89 ,  Y10T428/24802 ,  Y10T428/298

Abstract: Provided is a nanowire manufacturing method, comprising forming a plurality of grid patterns on a substrate, forming a nanowire on the grid patterns, and separating the grid pattern and the nanowire. According to the present invention, the width and height of the nanowire can be adjusted by controlling the wet-etching process time period, and the nanowire can be manufactured at a room temperature at low cost, the nanowire can be mass-manufactured and the nanowire with regularity can be manufactured even in case of mass production.

Abstract translation: 提供一种纳米线制造方法，包括在基板上形成多个格栅图案，在网格图案上形成纳米线，以及分离网格图案和纳米线。 根据本发明，可以通过控制湿蚀刻工艺时间段来调节纳米线的宽度和高度，并且可以以低成本在室温下制造纳米线，可以大量制造纳米线，并且纳米线 即使在大规模生产的情况下也可以制造。

公开(公告)号：US08786064B2

公开(公告)日：2014-07-22

申请号：US13361144

申请日：2012-01-30

Applicant: Jin Su Kim ,  Ji Man Ryu ,  Soon Gyu Yim

Inventor： Jin Su Kim ,  Ji Man Ryu ,  Soon Gyu Yim

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L24/83 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.

Abstract translation: 本文公开了一种半导体芯片，包括：在其一个表面上形成有凹部的第一基板和形成在凹部的底表面上的开口; 与第一基板的另一个表面接触的第二基板; 以及安装在凹部中的半导体芯片。

公开(公告)号：US20130271834A1

公开(公告)日：2013-10-17

申请号：US13976320

申请日：2011-10-11

Applicant: Jin Su Kim ,  Kyoung Jong Yoo ,  Young Jae Lee ,  Jun Lee

Inventor： Jin Su Kim ,  Kyoung Jong Yoo ,  Young Jae Lee ,  Jun Lee

IPC: G02B5/30

CPC classification number: G02B5/3058 ,  G02B5/008

Abstract: Provided is a wire grid polarizer including: a first grid patterns on a substrate; a second grid pattern on the first grid patterns; and a passivation layer filling between the first grid patterns and the second grid patterns.

Abstract translation: 提供一种线栅偏振器，包括：基板上的第一栅格图案; 第一网格图案上的第二网格图案; 以及填充在第一栅格图案和第二栅格图案之间的钝化层。

公开(公告)号：US20120255764A1

公开(公告)日：2012-10-11

申请号：US13500754

申请日：2010-08-05

Applicant: Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Chi Hee Ahn

Inventor： Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Chi Hee Ahn

IPC: H05K3/00 ,  G03F7/20 ,  H05K1/02

CPC classification number: H05K3/205 ,  H05K3/107 ,  H05K3/108 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/0355 ,  H05K2203/0108 ,  Y10T156/10

Abstract: An embedded printed circuit board and a manufacturing method thereof are provided. The manufacturing method includes a first step of forming a first insulating layer having a seed layer formed on one side thereof and at least. one metal pattern embedded therein and a second step of laminating the first insulating layer and a base substrate with an inner circuit having a second insulating layer interposed between the first insulating layer and the base substrate. Accordingly, a printed circuit board with a circuit embedded in an insulating layer is provided, and thus a high-density and high-reliability printed circuit board can be achieved. Furthermore, since the printed circuit board is manufactured using a mold, a circuit manufacturing process for embedding, a process for forming a seed layer and a complicated process such as surface grinding are omitted so as to simplify the manufacturing process.

Abstract translation: 提供一种嵌入式印刷电路板及其制造方法。 该制造方法包括：形成第一绝缘层的第一工序，该第一绝缘层的至少一面形成有种子层。 嵌入其中的一个金属图案，以及第二步骤，用第一绝缘层和基底衬底之间的具有第二绝缘层的内部电路层叠第一绝缘层和基底。 因此，提供了具有嵌入在绝缘层中的电路的印刷电路板，因此可以实现高密度和高可靠性的印刷电路板。 此外，由于使用模具制造印刷电路板，所以省略了用于嵌入的电路制造工艺，用于形成种子层的工艺和诸如表面磨削的复杂工艺，以简化制造工艺。