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    Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System
    11.
    发明申请
    Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System 有权
    包括立方体或四边形系统的绝缘层的半导体器件

    公开(公告)号：US20090085160A1

    公开(公告)日：2009-04-02

    申请号：US12238822

    申请日：2008-09-26

    Applicant: Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

    Inventor： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

    IPC: H01L29/92

    CPC classification number: H01L29/51 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/513

    Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

    Abstract translation: 本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。 半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及 其电连接到晶体管。 半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括 金属硅酸盐层。 绝缘层可以形成在下电极和上电极之间。

    Semiconductor memory device with hierarchical bit line structure
    12.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US07489570B2

    公开(公告)日：2009-02-10

    申请号：US11480447

    申请日：2006-07-05

    Applicant: Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    Inventor： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC: G11C7/00

    CPC classification number: G11C11/417 ,  G11C7/18 ,  G11C8/12

    Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    Abstract translation: 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

    METHOD OF FABRICATING METAL-INSULATOR-METAL CAPACITOR
    15.
    发明申请
    METHOD OF FABRICATING METAL-INSULATOR-METAL CAPACITOR 审中-公开
    金属绝缘体 - 金属电容器的制造方法

    公开(公告)号：US20070026625A1

    公开(公告)日：2007-02-01

    申请号：US11460916

    申请日：2006-07-28

    Applicant: Jung-Hee CHUNG ,  Jong-Cheol LEE ,  Jae-Hyoung CHOI ,  Jeong-Sik CHOI ,  Se-Hoon OH ,  Cha-Young YOO

    Inventor： Jung-Hee CHUNG ,  Jong-Cheol LEE ,  Jae-Hyoung CHOI ,  Jeong-Sik CHOI ,  Se-Hoon OH ,  Cha-Young YOO

    IPC: H01L21/473

    CPC classification number: H01L21/02181 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3142 ,  H01L21/3162 ,  H01L21/31645 ,  H01L28/91

    Abstract: In one embodiment, a method of fabricating a MIM capacitor includes forming an interlayer insulating layer having a contact plug on a semiconductor substrate, forming an etch stop layer on the interlayer insulating layer, and forming a mold layer having an opening exposing the contact plug on the etch stop layer. Next, a first conductive layer for the lower electrode is formed on the sidewalls and the bottom of the opening, and a photoresistive layer is formed on the first conductive layer. The mold layer and the photoresistive layer are then removed, and a composite dielectric layer is formed on the lower electrode. A second conductive layer is then formed on the composite dielectric layer. The composite dielectric layer may be composed of an oxide hafnium (HfO2) dielectric layer and an oxide aluminum (Al2O3) dielectric layer, with the oxide hafnium dielectric layer having a thickness of about 20 Å to about 50 Å. The oxide aluminum dielectric layer is formed with a thickness determined by subtracting the thickness of the oxide hafnium dielectric layer from a composite dielectric layer thickness corresponding to an equivalent oxide dielectric layer thickness set to provide a predetermined capacitance of the capacitor.

    Abstract translation: 在一个实施例中，制造MIM电容器的方法包括在半导体衬底上形成具有接触插塞的层间绝缘层，在层间绝缘层上形成蚀刻停止层，并形成具有露出接触插头的开口的模具层 蚀刻停止层。 接下来，在开口的侧壁和底部形成用于下电极的第一导电层，并且在第一导电层上形成光刻胶层。 然后去除模具层和光致抗蚀剂层，并且在下部电极上形成复合电介质层。 然后在复合电介质层上形成第二导电层。 复合电介质层可以由氧化铪（HfO 2/2）介电层和氧化铝（Al 2 O 3 3）介电层 氧化铪介电层的厚度约为20至50埃。 形成氧化铝介电层，其厚度通过从设置为提供电容器的预定电容的等效氧化物介电层厚度对应的复合电介质层厚度减去氧化铪电介质层的厚度而确定。

    Back light driving device
    16.
    发明申请
    Back light driving device 审中-公开
    背光驱动装置

    公开(公告)号：US20060097979A1

    公开(公告)日：2006-05-11

    申请号：US11200171

    申请日：2005-08-10

    Applicant: Kyoung-geun Lee ,  Jong-cheol Lee ,  Jung-seob Lee

    Inventor： Kyoung-geun Lee ,  Jong-cheol Lee ,  Jung-seob Lee

    IPC: G09G3/36

    CPC classification number: H05B41/2851 ,  H05B41/2855

    Abstract: A back light driving device having an inverter circuit connected with a lamp, the inverter circuit including a driving voltage generating unit provided with a plurality of lead parts, which is joined with a power input unit and a switch unit for supplying a driving voltage to the lamp, wherein each of the lead parts includes a plurality of lead terminals. Accordingly, the back light driving device is capable of preventing malfunctions due to disconnections or poor lead terminal junctions of the driving voltage generating unit.

    Abstract translation: 一种具有与灯连接的逆变器电路的背光驱动装置，所述逆变器电路包括驱动电压产生单元，所述驱动电压产生单元设置有多个引线部分，所述驱动电压产生单元与电源输入单元和用于向所述驱动电压提供驱动电压的开关单元连接 灯，其中每个引线部分包括多个引线端子。 因此，背光驱动装置能够防止由于驱动电压产生单元的断开或引线端子接点不良引起的故障。

    Method and circuit for writing double data rate (DDR) sampled data in a memory device
    18.
    发明申请
    Method and circuit for writing double data rate (DDR) sampled data in a memory device 失效
    用于在存储器件中写入双倍数据速率（DDR）采样数据的方法和电路

    公开(公告)号：US20050157827A1

    公开(公告)日：2005-07-21

    申请号：US11037602

    申请日：2005-01-18

    Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

    Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

    IPC: G11C11/417 ,  G11C7/10 ,  G11C11/40 ,  H04L7/00

    CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

    Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

    Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

    Semiconductor memory device having echo clock path
    19.
    发明授权
    Semiconductor memory device having echo clock path 有权
    具有回波时钟路径的半导体存储器件

    公开(公告)号：US06459652B1

    公开(公告)日：2002-10-01

    申请号：US09996225

    申请日：2001-11-28

    Applicant: Jong Cheol Lee ,  Kwang Jin Lee

    Inventor： Jong Cheol Lee ,  Kwang Jin Lee

    IPC: G11C800

    CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C29/14

    Abstract: A semiconductor memory device effectively capable of removing skew between data output of a data output circuit and an echo clock of an echo clock generator is provided. The semiconductor memory device comprises a delay circuit comprising a plurality of delay paths for delaying the data enable clock by different time, a test controller for generating a mode select signal and a delay path test signal in response to a test code signal, and a delay signal selection circuit comprising a plurality of fuses for producing a default delay path select signal based on a programmed state of the plurality of fuses, and a multiplexer, responsive to the mode select signal, for selectively providing the default delay path select signal or the delay path test signal to the delay circuit.

    Abstract translation: 提供了有效地消除数据输出电路的数据输出与回波时钟发生器的回波时钟之间的偏差的半导体存储器件。 半导体存储器件包括延迟电路，该延迟电路包括多个用于将数据使能时钟延迟不同时间的延迟路径，用于响应于测试代码信号产生模式选择信号和延迟路径测试信号的测试控制器以及延迟 信号选择电路，包括多个保险丝，用于基于多个保险丝的编程状态产生默认延迟路径选择信号;以及复用器，响应于模式选择信号，用于选择性地提供默认延迟路径选择信号或延迟 路径测试信号到延迟电路。

    Device for sensing food weight in a microwave oven
    20.
    发明授权
    Device for sensing food weight in a microwave oven 失效
    用于在微波炉中感测食物重量的装置

    公开(公告)号：US5712451A

    公开(公告)日：1998-01-27

    申请号：US462288

    申请日：1995-06-05

    Applicant: Jong Cheol Lee

    Inventor： Jong Cheol Lee

    IPC: G01G3/00 ,  F24C7/02 ,  G01G7/06 ,  G01G19/52 ,  G01G19/56 ,  H05B6/64 ,  H05B6/80 ,  G01G3/14 ,  H05B1/02 ,  H05B6/50

    CPC classification number: H05B6/6411 ,  G01G19/56 ,  G01G7/06 ,  H05B6/6464

    Abstract: A device for sensing food weight in a microwave oven includes a bracket formed into one body and mounted with a motor assembly having a motor axis, a movable electrode plate fixed to an extending piece separated from the bottom of the bracket and a printed circuit board in which a fixed electrode plate is printed. The printed circuit board is inserted in a space formed between the bottom of the bracket and the movable electrode plate. An initial food weight is set by varying an overlapping area of the movable electrode plate and the fixed electrode plate. The food weight is sensed by using the distance variation between the movable electrode plate and the fixed electrode plate. Since no weight is applied to the printed circuit board, the deformation and the destruction of the printed circuit board is prevented. Further, the distance between the fixed electrode plate and the movable electrode plate may be maintained constantly.

    Abstract translation: 用于感测微波炉中的食物的装置包括形成为一体并且安装有具有电动机轴的电动机组件的支架，固定到与支架的底部分离的延伸件的可动电极板和印刷电路板 打印固定电极板。 印刷电路板插入形成在托架的底部和可动电极板之间的空间中。 通过改变可动电极板和固定电极板的重叠区域来设定初始食物重量。 通过使用可动电极板和固定电极板之间的距离变化来感测食物重量。 由于不对印刷电路板施加重量，因此可以防止印刷电路板的变形和破坏。 此外，固定电极板和可动电极板之间的距离可以恒定地保持。

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