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    Semiconductor memory device
    11.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5726930A

    公开(公告)日：1998-03-10

    申请号：US653236

    申请日：1996-05-24

    Applicant: Masatoshi Hasegawa ,  Kazuhiko Kajigaya ,  Kan Takeuchi ,  Katsumi Matsuno ,  Osamu Nagashima

    Inventor： Masatoshi Hasegawa ,  Kazuhiko Kajigaya ,  Kan Takeuchi ,  Katsumi Matsuno ,  Osamu Nagashima

    IPC: G11C14/00 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: G11C11/22 ,  G11C11/404

    Abstract: A semiconductor memory device capable of simultaneously providing volatile and non-volatile portions is disclosed having a plurality of memory mats, and a plurality of plate electrodes and a plurality of memory mats each provided in one-to-one correspondence with the memory maps. The memory mats each include a plurality of word lines, a plurality of bit lines and a plurality of memory cells provided at the intersections of the word lines and the bit lines. The memory cells each include an information storage capacitor having a ferroelectric film, and an address selection MOSFET. The information storage capacitor has a pair of electrodes, one of which is connected to the plate electrode that corresponds to the memory mat in which the information storage capacitor is included. A first voltage or a second voltage is selectively applied to each of the plate electrodes according to data held in the memory circuit corresponding to the plate electrode. When the first voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made incapable of polarization reversal irrespective of a binary write signal given to the bit lines. When the second voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made capable of polarization inversion in response to a binary write signal given to the bit lines.

    Abstract translation: 公开了能够同时提供易失性和非易失性部分的半导体存储器件，其具有多个存储器垫，以及多个板电极和多个存储器垫，每个存储垫与存储器映射图一一对应地提供。 存储器垫每个都包括多个字线，多个位线和设置在字线和位线的交点处的多个存储单元。 存储单元各自包括具有铁电膜的信息存储电容器和地址选择MOSFET。 信息存储电容器具有一对电极，其中一个电极连接到对应于包括信息存储电容器的存储器垫的平板电极。 根据与平板电极相对应的存储电路中保存的数据，选择性地向每个平板电极施加第一电压或第二电压。 当第一电压施加到平板电极时，连接到平板电极的信息存储电容器不会产生极化反转，而与给定位线的二进制写入信号无关。 当第二电压施加到平板电极时，连接到平板电极的信息存储电容器响应于给定位线的二进制写入信号而能够进行极化反转。

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