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    Receiver and Wireless Communication Apparatus
    11.
    发明申请
    Receiver and Wireless Communication Apparatus 失效
    接收机和无线通信设备

    公开(公告)号：US20080254756A1

    公开(公告)日：2008-10-16

    申请号：US11568365

    申请日：2006-09-25

    Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

    Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

    IPC: H04B1/16 ,  H04B1/38

    CPC classification number: H04L27/2272 ,  H03C3/0966 ,  H03D3/242 ,  H04B1/38 ,  H04L27/2273 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0055 ,  H04W56/00 ,  H04W88/02 ,  Y02D70/1222 ,  Y02D70/40

    Abstract: A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

    Abstract translation: 一种接收器具有：第一电压控制振荡器，被配置为产生第一振荡信号;第二压控振荡器，被配置为产生具有第一相位的第二振荡信号;第一相位比较器，被配置为检测第一和第二振荡信号之间的相位差; 解调器，被配置为执行所述接收信号的解调处理并生成包括在所述第一振荡信号中的第二相位的定时信息;第二相位比较器，被配置为检测所述第一和第二振荡信号之间的相位差;以及第一控制 电压发生器被配置为基于由第二相位比较器检测的相位差产生用于控制第二压控振荡器的相位和频率的第一控制电压。

    METHOD FOR FABTRICATING SEMICONDUCTOR DEVICE
    12.
    发明申请
    METHOD FOR FABTRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20080206924A1

    公开(公告)日：2008-08-28

    申请号：US11963485

    申请日：2007-12-21

    Applicant: Kazuhide ABE

    Inventor： Kazuhide ABE

    IPC: H01L21/20

    CPC classification number: H01L29/6606 ,  H01L21/0465

    Abstract: According to the first aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove in the periphery of a region on the silicon carbide film in which crystal defects are aggregated.According to the second aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove on said silicon carbide film so that a region in which crystal defects are aggregated in said silicon carbide film is removed.

    Abstract translation: 根据本发明的第一方面，一种制造具有碳化硅（SiC）膜的半导体器件的方法包括在衬底上生长碳化硅膜的工艺; 以及在晶圆缺陷聚集的碳化硅膜上的区域的周围形成槽的工序。 根据本发明的第二方面，制造具有碳化硅（SiC）膜的半导体器件的方法包括在衬底上生长碳化硅膜的工艺; 以及在所述碳化硅膜上形成凹槽的过程，从而去除在所述碳化硅膜中晶体缺陷聚集的区域。

    Method of forming copper wire
    15.
    发明授权
    Method of forming copper wire 有权
    铜线形成方法

    公开(公告)号：US07144812B2

    公开(公告)日：2006-12-05

    申请号：US10748254

    申请日：2003-12-31

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/44

    CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76858 ,  H01L21/76867

    Abstract: Cu is nitrided to form a nitride of Cu 5 on a Cu wiring layer 1. A diffusion base material layer 6 used as a diffusion source and a barrier metal layer 7, which are interdiffused with Cu, are formed on the nitride of Cu 5. With heat treatment, the Cu wiring layer 1 and the diffusion base material layer 6 are interdiffused to form an alloy layer of Cu 8 between the Cu wiring layer 1 and the barrier metal layer 7.

    Abstract translation: Cu在Cu布线层1上被氮化以形成Cu 5的氮化物。 在Cu 5的氮化物上形成有用作扩散源的扩散基材层6和与Cu相互扩散的阻挡金属层7。 通过热处理，Cu配线层1和扩散基材层6相互扩散，在Cu配线层1和阻挡金属层7之间形成Cu 8的合金层。

    Hybrid memory device and method for manufacturing the same
    16.
    发明申请
    Hybrid memory device and method for manufacturing the same 失效
    混合存储装置及其制造方法

    公开(公告)号：US20060065917A1

    公开(公告)日：2006-03-30

    申请号：US11228188

    申请日：2005-09-19

    Applicant: Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

    Inventor： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

    IPC: H01L29/94

    CPC classification number: H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

    Abstract: A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

    Abstract translation: 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

    Semiconductor device and a method of manufacturing the same
    17.
    发明申请
    Semiconductor device and a method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20060024906A1

    公开(公告)日：2006-02-02

    申请号：US11116190

    申请日：2005-04-28

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/20

    CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7687 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/40

    Abstract: The present invention provides a semiconductor device, having: a semiconductor substrate; a first electrode formed over the semiconductor substrate; a first insulation film covering the first electrode and having an aperture for exposing a part of the first electrode; a first conductive film formed on a part of the first insulation film and the first electrode inside the aperture; an isolation region placed inside the aperture; and a second conductive film formed on the first conductive film and the isolation region.

    Abstract translation: 本发明提供一种半导体器件，具有：半导体衬底; 形成在半导体衬底上的第一电极; 覆盖所述第一电极并具有用于暴露所述第一电极的一部分的孔的第一绝缘膜; 形成在第一绝缘膜的一部分上的第一导电膜和孔内的第一电极; 放置在孔内的隔离区; 以及形成在第一导电膜和隔离区上的第二导电膜。

    Tunable filter and portable telephone
    18.
    发明申请
    Tunable filter and portable telephone 失效
    可调滤波器和便携式电话

    公开(公告)号：US20050212612A1

    公开(公告)日：2005-09-29

    申请号：US11039872

    申请日：2005-01-24

    Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Yoshida ,  Hiroshi Tsurumi

    Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Yoshida ,  Hiroshi Tsurumi

    IPC: H01G7/06 ,  H03B5/00 ,  H03H7/075 ,  H03H7/12 ,  H03H9/00 ,  H03H9/17 ,  H03H9/46 ,  H03H9/54 ,  H03H9/58 ,  H03H9/60 ,  H03H9/64 ,  H03H11/04 ,  H03J1/00 ,  H03J3/08

    CPC classification number: H03J3/08 ,  H03H9/542 ,  H03H9/605 ,  H03H2210/012 ,  H03H2210/015 ,  H03J1/0008

    Abstract: A tunable filter has a plurality of variable capacitors and a plurality of inductor elements, each being formed on a common substrate, a filter circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a monitor circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a detecting circuit which detects a prescribed circuit constant of the monitor circuit, a storage which stores information relating to a reference circuit constant of the monitor circuit, and a capacitance control circuit which controls capacitance of the variable capacitors in the monitor circuit and capacitance of the variable capacitors in the filter circuit, based on a result detected by the detecting circuit and information stored in the storage.

    Abstract translation: 可调谐滤波器具有多个可变电容器和多个电感器元件，每个电感器元件形成在公共基板上，通过使用多个可变电容器的至少一部分和多个电感器元件的一部分形成的滤波器电路， 通过使用多个可变电容器的至少一部分和多个电感器元件的一部分形成的监视电路，检测监视电路的规定电路常数的检测电路，存储与参考电路有关的信息的存储器 基于由检测电路检测的结果和存储在存储器中的信息，控制监视电路中的可变电容器的电容和滤波器电路中的可变电容器的电容的电容控制电路。

    Thin film piezoelectric actuator
    19.
    发明申请
    Thin film piezoelectric actuator 失效
    薄膜压电致动器

    公开(公告)号：US20050194867A1

    公开(公告)日：2005-09-08

    申请号：US11054404

    申请日：2005-02-10

    Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

    Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

    IPC: H01L41/09 ,  H01G7/06 ,  H01L41/053 ,  H01L41/08 ,  H01L41/18 ,  H01L41/187 ,  H01L41/22 ,  H01L41/29 ,  H01L41/316

    CPC classification number: H01G7/06 ,  H01H2057/006 ,  H01L41/0933 ,  H01L41/094

    Abstract: A thin film piezoelectric actuator comprises a driving part at least one end of which is supported by an anchor portion. The driving part includes: a piezoelectric film, a first lower electrode provided under a first region of the piezoelectric film, a second lower electrode provided under a second region different from the first region of the piezoelectric film, a first upper electrode provided opposite to the first lower electrode on the piezoelectric film, a second upper electrode provided opposite to the second lower electrode on the piezoelectric film, a first connection part that electrically connects the first lower electrode and the second upper electrode via a first via hole formed in the piezoelectric film, and a second connection part that electrically connects the second lower electrode and the first upper electrode via a second via hole formed in the piezoelectric film.

    Abstract translation: 薄膜压电致动器包括驱动部件，其至少一端由锚固部分支撑。 驱动部包括：压电膜，设置在压电膜的第一区域下方的第一下电极，设置在与压电膜的第一区不同的第二区域下方的第二下电极，与第一下电极相对设置的第一上电极 压电膜上的第一下电极，与压电膜上的第二下电极相对设置的第二上电极，经由形成在压电膜中的第一通孔电连接第一下电极和第二上电极的第一连接部 以及第二连接部，其经由形成在所述压电膜中的第二通路孔电连接所述第二下部电极和所述第一上部电极。

    Method of forming buried wiring in semiconductor device
    20.
    发明申请
    Method of forming buried wiring in semiconductor device 失效

    公开(公告)号：US20050009319A1

    公开(公告)日：2005-01-13

    申请号：US10765155

    申请日：2004-01-28

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC classification number: H01L21/7685 ,  H01L21/7684 ,  H01L21/76867

    Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

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