公开(公告)号：US06225160B1

公开(公告)日：2001-05-01

申请号：US09295067

申请日：1999-04-20

Applicant: Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

Inventor： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

Abstract: A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

Abstract translation: 一种制造电容器的底部电极的方法。 在基板上形成第一电介质层。 在第一电介质层上形成覆盖层。 在盖层上形成第二电介质层。 形成节点接触孔以穿透第二介电层，盖层和第一介电层。 衬垫层形成在节点接触孔的侧壁上。 在第二电介质层上形成限制层。 在限制层的一部分上形成有图案的导电层，并填充节点接触孔。 在图案化的导电层上形成选择性半球形纹理层。

公开(公告)号：US06221712B1

公开(公告)日：2001-04-24

申请号：US09385805

申请日：1999-08-30

Applicant: Kuo-Tai Huang ,  Michael W C Huang ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Michael W C Huang ,  Tri-Rung Yew

IPC: B32B1900

CPC classification number: H01L21/28194 ,  C23C16/405 ,  H01L21/28088 ,  H01L21/31604 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.

Abstract translation: 一种用于制造栅极结构的方法。 该方法包括提供衬底，随后在衬底的表面上形成氮化物区域。 使用钽（Ta）基有机化合物和作为前体的钛（Ti）基有机化合物，进行有机金属化学气相沉积（OMCVD），从而在衬底上形成Ta2-xTixO5电介质层。 然后依次在Ta2-xTixO5电介质层上形成阻挡层，导电层和抗反射（AR）层。 随后，将AR层，导电层，阻挡层和Ta2-xTixO5电介质层定义为在氮化物区域的衬底上形成栅极结构。 在这种情况下，Ta类有机化合物可以包括Ta-醇盐化合物，而Ti基有机化合物可以包括Ti-醇盐化合物或Ti-酰胺化合物。

公开(公告)号：US06207497B1

公开(公告)日：2001-03-27

申请号：US09565782

申请日：2000-05-05

Applicant: Kuo-Tai Huang ,  Juan-Yuan Wu

Inventor： Kuo-Tai Huang ,  Juan-Yuan Wu

IPC: H01L218242

CPC classification number: H01L21/3185 ,  H01L27/10852 ,  H01L28/84

Abstract: The present invention relates to a method for forming excellent conformity due to improved surface sensitivity. A substrate is providing on which a transistor is formed. Moreover, a blanket first dielectric layer is deposited over the substrate. Then, a first photoresist layer is formed over the dielectric layer, wherein the first photoresist layer is defined and etched to form a contact opening. Further, a first conductive layer is formed to fill the contact opening, and performing an etching process to remove the first conductive layer to form a node contact. Consequentially, a second conductive layer is deposited over the first dielectric layer and the node contact. A second photoresist layer is formed over the second conductive layer, wherein the second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor. Next, a hemispherical silicon grain (HSG) is formed over and on a sidewall of the second conductive layer. Treating the hemispherical silicon grain (HSG) layer by rapid thermal nitration (RTN). And then a conformal second dielectric layer is deposited over the hemispherical silicon grain (HSG) and the first dielectric layer after rapid thermal nitration (RTN). Finally, a blanket third conductive layer is formed over the substrate to serve as an upper electrode of the capacitor.

Abstract translation: 本发明涉及由于提高表面灵敏度而形成优异的一致性的方法。 提供其上形成晶体管的衬底。 此外，毯子第一介电层沉积在衬底上。 然后，在电介质层上形成第一光致抗蚀剂层，其中限定和蚀刻第一光致抗蚀剂层以形成接触开口。 此外，形成第一导电层以填充接触开口，并且执行蚀刻工艺以去除第一导电层以形成节点接触。 因此，第二导电层沉积在第一介电层和节点接触之上。 在第二导电层上形成第二光致抗蚀剂层，其中限定和蚀刻第二光致抗蚀剂层以形成作为电容器的上电极的存储节点。 接下来，在第二导电层的侧壁上形成半球形硅晶粒（HSG）。 通过快速热硝化（RTN）处理半球形硅晶粒（HSG）层。 然后在快速热硝化（RTN）之后，半球形硅晶粒（HSG）和第一介电层上沉积共形第二介电层。 最后，在衬底上形成覆盖的第三导电层以用作电容器的上电极。

公开(公告)号：US06200844B1

公开(公告)日：2001-03-13

申请号：US09249503

申请日：1999-02-12

Applicant: Kuo-Tai Huang

Inventor： Kuo-Tai Huang

IPC: H01L218234

CPC classification number: H01L28/40 ,  H01L21/3185 ,  H01L27/1085 ,  H01L28/56

Abstract: A method of manufacturing a dielectric film for a capacitor in a DRAM. A native oxide layer is removed using a rapid ramp process at a pressure lower than 10−5 torr. A nitridation is performed to form a dielectric layer on the surface of a storage electrode. A silicon nitride layer is formed on the dielectric layer. The rapid ramp process is started at a temperature of about 450-550° C. The temperature is raised at a rate of about 80-120° C./minute. The rapid ramp process is stopped at about 700-850° C. The nitridation is performed using a source gas, such as ammonia at about 700-850° C. for a relatively long time of about 10-60 minutes. The dielectric layer includes silicon nitride or silicon-oxy-nitride. An oxide layer is further formed on the silicon nitride layer. The oxide layer is formed by, for example, a rapid thermal process. A gas used in the rapid thermal process can be selected from a group including nitrogen monoxide (N2O), oxygen and combinations of nitrogen monoxide (N2O) and oxygen. The dielectric film structure of the capacitor of the invention can be a double-layer structure such as silicon nitride/silicon oxide or a mono-layer structure, such as silicon nitride.

Abstract translation: 制造DRAM中的电容器用电介质膜的方法。 在低于10-5乇的压力下使用快速斜坡过程去除天然氧化物层。 进行氮化以在存储电极的表面上形成电介质层。 在电介质层上形成氮化硅层。 快速斜坡过程在约450-550℃的温度下开始。温度以约80-120℃/分钟的速率升高。 快速斜坡过程在约700-850℃停止。氮化在约700-850℃下使用源气体，例如氨进行约10-60分钟的较长时间。 电介质层包括氮化硅或氮氧化硅。 在氮化硅层上进一步形成氧化物层。 氧化物层通过例如快速热处理形成。 用于快速热处理的气体可以选自包括一氧化氮（N2O），氧气和一氧化氮（N2O）和氧气的组合的组。 本发明的电容器的电介质膜结构可以是诸如氮化硅/氧化硅的双层结构或诸如氮化硅的单层结构。

公开(公告)号：US6156600A

公开(公告)日：2000-12-05

申请号：US195173

申请日：1998-11-17

Applicant: Fang-Ching Chao ,  Wen-Yi Hsieh ,  Kuo-Tai Huang

Inventor： Fang-Ching Chao ,  Wen-Yi Hsieh ,  Kuo-Tai Huang

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC classification number: H01L28/40 ,  H01L21/31604 ,  H01L28/56

Abstract: A method for fabricating a capacitor in an integrated circuit, using tantalum oxide as the dielectric layer to obtain a higher capacitance. A barrier layer is formed between the polysilicon layer and the tantalum oxide layer to prevent the formation of a silicon oxide layer. Thus, that capacitance of the capacitor is not reduced by the additional thickness of the silicon oxide layer.

Abstract translation: 一种用于在集成电路中制造电容器的方法，其使用氧化钽作为电介质层以获得更高的电容。 在多晶硅层和氧化钽层之间形成阻挡层，以防止形成氧化硅层。 因此，电容器的电容量不会被氧化硅层的附加厚度减小。

公开(公告)号：US6087262A

公开(公告)日：2000-07-11

申请号：US189140

申请日：1998-11-09

Applicant: Gwo-Shii Yang ,  Kuo-Tai Huang ,  Tri-Rung Yew ,  Water Lur

Inventor： Gwo-Shii Yang ,  Kuo-Tai Huang ,  Tri-Rung Yew ,  Water Lur

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/00

CPC classification number: H01L21/31053 ,  H01L21/76229

Abstract: A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.

Abstract translation: 用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。 此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

公开(公告)号：US5976951A

公开(公告)日：1999-11-02

申请号：US106746

申请日：1998-06-30

Applicant: Kuo-Tai Huang ,  Chih-Hsiang Hsiao ,  Chao-Yen Chen

Inventor： Kuo-Tai Huang ,  Chih-Hsiang Hsiao ,  Chao-Yen Chen

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76232 ,  Y10S148/05

Abstract: A method for forming an isolating trench in a substrate is disclosed herein. The forgoing method includes the following steps. First, form a first dielectric layer and a second dielectric layer on the substrate subsequently, and then develop a photoresist pattern on the second dielectric layer. Then, etch the substrate, the first dielectric layer and the second dielectric layer to form a trench in the substrate. Next, form a first silicon dioxide layer in the trench followed by removing the photoresist pattern. The next step is to form a third dielectric layer on the second dielectric layer and the first silicon dioxide layer. Subsequently, fill the trench with silicon dioxide to from an oxide trench; then remove the second dielectric layer, a first portion of the third dielectric layer and a portion of the oxide trench with a chemical mechanical polishing (CMP) and a first solution. The third dielectric layer mentioned above includes the first portion of the third dielectric layer and a second portion of the third dielectric layer. Finally, etch the first dielectric layer and the oxide trench to expose the substrate. The second portion of the third dielectric layer is used to prevent an oxide loss in the oxide trench; then the isolating trench being formed thereof.

Abstract translation: 本文公开了在衬底中形成隔离沟槽的方法。 前述方法包括以下步骤。 首先，随后在衬底上形成第一电介质层和第二电介质层，然后在第二电介质层上形成光致抗蚀剂图案。 然后，蚀刻衬底，第一介电层和第二介电层，以在衬底中形成沟槽。 接下来，在沟槽中形成第一二氧化硅层，然后除去光致抗蚀剂图案。 下一步是在第二电介质层和第一二氧化硅层上形成第三电介质层。 随后，用二氧化硅填充沟槽至氧化物沟槽; 然后通过化学机械抛光（CMP）和第一溶液去除第二介电层，第三介电层的第一部分和氧化物沟槽的一部分。 上述第三电介质层包括第三电介质层的第一部分和第三电介质层的第二部分。 最后，蚀刻第一介电层和氧化物沟槽以暴露衬底。 第三介质层的第二部分用于防止氧化物沟槽中的氧化物损失; 则形成隔离槽。

公开(公告)号：US08853068B2

公开(公告)日：2014-10-07

申请号：US13329877

申请日：2011-12-19

Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

公开(公告)号：US08551837B2

公开(公告)日：2013-10-08

申请号：US13408016

申请日：2012-02-29

Applicant: Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin ,  Yu Chao Lin

Inventor： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin ,  Yu Chao Lin

IPC: H01L21/8242

CPC classification number: H01L21/823828 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

Abstract translation: 公开了制造具有高k /金属栅极特征的半导体器件的方法。 在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。 在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

公开(公告)号：US20120225529A1

公开(公告)日：2012-09-06

申请号：US13465551

申请日：2012-05-07

Applicant: Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。