公开(公告)号：US09397219B2

公开(公告)日：2016-07-19

申请号：US14680458

申请日：2015-04-07

Applicant: Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

Abstract translation: 半导体器件包括能够对包括在器件中的晶体管的沟道区域施加应变的应变诱导层以及该器件的制造方法。 半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并且沿着第一方向布置在所述沟道区的两侧; 以及设置在通道区域上的栅极结构。 栅极结构包括沿与第一方向不同的第二方向延伸的栅极电极图案，沟道区域和栅电极图案之间的栅极介电层以及覆盖栅电极图案的各个侧表面的栅极间隔 栅介质层。 源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。 第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

公开(公告)号：US09368495B2

公开(公告)日：2016-06-14

申请号：US14576368

申请日：2014-12-19

Applicant: Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L21/00 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

Abstract translation: 半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层， 多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

公开(公告)号：US20150333061A1

公开(公告)日：2015-11-19

申请号：US14576368

申请日：2014-12-19

Applicant: Seok-Hoon KIM ,  Jin-Bum KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Cho-Eun LEE ,  Jin-Hee HAN ,  Bon-Young KOO

Inventor： Seok-Hoon KIM ,  Jin-Bum KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Cho-Eun LEE ,  Jin-Hee HAN ,  Bon-Young KOO

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

Abstract translation: 半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层， 多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

公开(公告)号：US08409947B2

公开(公告)日：2013-04-02

申请号：US12693080

申请日：2010-01-25

Applicant: Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

Inventor： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

IPC: H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

Abstract translation: 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

公开(公告)号：US08361860B2

公开(公告)日：2013-01-29

申请号：US12656130

申请日：2010-01-19

Applicant: Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

Inventor： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

IPC: H01L21/8242

CPC classification number: H01L21/7687 ,  H01L27/10855 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

Abstract translation: 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

公开(公告)号：US20160358925A1

公开(公告)日：2016-12-08

申请号：US15084785

申请日：2016-03-30

Applicant: Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

Inventor： Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Abstract translation: 半导体器件包括衬底，衬底上的鳍状有源区域图案，包括上部区域和下部区域的鳍状主动区域图案，围绕鳍状物区域图案的器件隔离层图案，在上部区域上的栅极图案 翅片有源区域图案和在翅片有源区域图案的下部区域上的应力器，其中，器件隔离层图案的顶表面比上部区域的顶表面低，并且高于下部区域的顶表面 。

公开(公告)号：US20160343858A1

公开(公告)日：2016-11-24

申请号：US14990863

申请日：2016-01-08

Applicant: Yoon Hae KIM ,  Jin Wook LEE ,  Jong Ki JUNG ,  Myung II KANG ,  Kwang Yong YANG ,  Kwan Heum LEE ,  Byeong Chan LEE

Inventor： Yoon Hae KIM ,  Jin Wook LEE ,  Jong Ki JUNG ,  Myung II KANG ,  Kwang Yong YANG ,  Kwan Heum LEE ,  Byeong Chan LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，第一区域中的多个第一栅极结构，第一栅极结构彼此间隔第一距离，第二栅极结构在第二区域中形成多个第二栅极结构 所述第二栅极结构彼此间隔开第二距离，所述第一栅极结构的侧壁上的第一间隔物，所述第一间隔物上的介电层，所述第二栅极结构的侧壁上的第二间隔物， 间隔物在第二间隔物上。

公开(公告)号：US20160027918A1

公开(公告)日：2016-01-28

申请号：US14741454

申请日：2015-06-17

Applicant: Nam Kyu KIM ,  Dong Chan SUH ,  Kwan Heum LEE ,  Byeong Chan LEE ,  Cho Eun LEE ,  Su Jin JUNG ,  Gyeom KIM ,  Ji Eon YOON

Inventor： Nam Kyu KIM ,  Dong Chan SUH ,  Kwan Heum LEE ,  Byeong Chan LEE ,  Cho Eun LEE ,  Su Jin JUNG ,  Gyeom KIM ,  Ji Eon YOON

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7834

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Abstract translation: 半导体器件可以包括：半导体衬底，嵌入在半导体衬底内并限定有源区的器件隔离层，形成在有源区中的沟道区，设置在沟道区上方的栅电极，设置在栅极绝缘层之间的栅极绝缘层 沟道区和栅电极以及与有源区内的沟道区相邻的硅锗外延层，并且包括含有第一浓度的锗的第一外延层，含有第二浓度的锗的第二外延层，高于第一 浓度，并且含有低于第二浓度的第三浓度的锗的第三外延层，第一至第三外延层按顺序依次堆叠在一起。

公开(公告)号：US08716093B2

公开(公告)日：2014-05-06

申请号：US13428900

申请日：2012-03-23

Applicant: Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

Inventor： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC: H01L21/336 ,  H01L21/338 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Abstract translation: 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US08431462B2

公开(公告)日：2013-04-30

申请号：US13183630

申请日：2011-07-15

Applicant: Kwan-Heum Lee ,  Soon-Wook Jung ,  Jung-Hyun Park ,  Wook-Je Kim ,  Jong-Sang Ban

Inventor： Kwan-Heum Lee ,  Soon-Wook Jung ,  Jung-Hyun Park ,  Wook-Je Kim ,  Jong-Sang Ban

IPC: H01L21/337 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/12

CPC classification number: H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅极结构; 形成牺牲隔离物可以形成在栅极衬底的侧壁上; 通过使用栅极结构和牺牲隔离物作为离子注入掩模的第一离子注入工艺将第一杂质注入到衬底的部分中以形成源区和漏区; 去除牺牲隔离物; 以及通过使用所述栅极结构作为离子注入掩模的第二离子注入工艺将第二杂质和碳原子注入到所述衬底的部分中，以分别形成源极和漏极延伸区域和碳掺杂区域。