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    Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper
    11.
    发明授权
    Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper 失效
    使用图案化蚀刻阻挡件制造具有双镶嵌线结构的半导体器件的方法

    公开(公告)号：US06498092B2

    公开(公告)日：2002-12-24

    申请号：US09780830

    申请日：2001-02-09

    Applicant: Kyung-tae Lee ,  Seong-ho Liu

    Inventor： Kyung-tae Lee ,  Seong-ho Liu

    IPC: H01L214763

    CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.

    Abstract translation: 公开了一种具有双镶嵌线结构的半导体器件及其制造方法。 半导体器件和方法解决了部分或完全闭合的接触孔的常规问题，并且通过使用蚀刻停止层，由于其介电常数的增加而抑制了层间绝缘层中的寄生电容的增加 。 为了实现这一点，在其上形成有第一导电图案的半导体衬底上形成第一层间绝缘层。 接下来，相对于第一层间绝缘层具有蚀刻选择比的蚀刻停止图案部分地形成在特定区域中。 此后，形成第二层间绝缘层和由铜制成的第二导电层。

    Method of fabricating damascene metal wiring
    15.
    发明授权
    Method of fabricating damascene metal wiring 失效
    制造镶嵌金属布线的方法

    公开(公告)号：US06492260B1

    公开(公告)日：2002-12-10

    申请号：US09447466

    申请日：1999-11-22

    Applicant: Young-wug Kim ,  Kyung-tae Lee

    Inventor： Young-wug Kim ,  Kyung-tae Lee

    IPC: H01L214763

    CPC classification number: H01L21/7684 ,  H01L21/76834

    Abstract: A method of forming damascene wiring without dishing and erosion employs a dummy layer to slow or delay polishing in selected regions and thereby prevent dishing and erosion of the damascene wiring. The dummy layer is above wide damascene regions and areas containing closely packed damascene regions. Therefore, non-uniform sheet resistance of the damascene metal wiring and electro-migration due to an increase in the local current density of the metal wiring can be prevented.

    Abstract translation: 在不进行凹陷和侵蚀的情况下形成镶嵌布线的方法使用虚拟层来减缓或延迟所选区域中的抛光，从而防止镶嵌布线的凹陷和侵蚀。 虚拟层位于宽大的镶嵌区域和包含紧密堆积的镶嵌区域的区域之上。 因此，可以防止由金属布线的局部电流密度的增加引起的非镶嵌金属布线的非均匀的薄层电阻和电迁移。

    Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same
    16.
    发明授权
    Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same 有权
    空隙边界结构，具有空隙边界结构的半导体器件及其形成方法

    公开(公告)号：US08420524B2

    公开(公告)日：2013-04-16

    申请号：US13067004

    申请日：2011-05-02

    Applicant: Cheong-Sik Yu ,  Kyung-Tae Lee

    Inventor： Cheong-Sik Yu ,  Kyung-Tae Lee

    IPC: H01L21/4763

    CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections.

    Abstract translation: 提供空隙边界结构，具有空隙边界结构的半导体器件及其形成方法。 结构，半导体器件和方法通过在互连之间形成空隙来提供减少互连之间的寄生电容的方法。 互连可以形成在半导体衬底上。 每个互连的上部宽度可以比其较低的宽度宽。 可以形成包含互连的成型层。 可以形成覆盖模制层的空隙边界层以限定互连之间的空隙。

    Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same
    17.
    发明授权
    Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same 有权
    具有高静电容量的电容器，包括该电容器的集成电路器件及其制造方法

    公开(公告)号：US07579643B2

    公开(公告)日：2009-08-25

    申请号：US11706972

    申请日：2007-02-16

    Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

    Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

    Abstract translation: 电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。 第一电极可以包括至少一个第一电极分支。 第二电极可面向第一电极并且包括至少一个第二电极分支。 低电介质层可以形成在第一电极分支和第二电极分支之间。 高电介质层可以形成在第一电极分支和第二电极分支之间。 高介电层可以具有比低介电层更高的介电常数。

    Cooling arrangement for centering device and spline shaft
    18.
    发明授权
    Cooling arrangement for centering device and spline shaft 失效
    定心装置和花键轴的冷却装置

    公开(公告)号：US07547207B2

    公开(公告)日：2009-06-16

    申请号：US11695409

    申请日：2007-04-02

    Applicant: Mihai Berceanu ,  Jeffrey Ngai ,  Filippo Martino ,  Vincent Travaglini ,  Kyung-Tae Lee ,  Gary Fong

    Inventor： Mihai Berceanu ,  Jeffrey Ngai ,  Filippo Martino ,  Vincent Travaglini ,  Kyung-Tae Lee ,  Gary Fong

    IPC: B29C45/74

    CPC classification number: B29C45/2606 ,  B29C45/32 ,  B29C45/73

    Abstract: A cooling arrangement is provided for a mold centering device for multi-level stack molds having a spline shaft with a central region journaled to an intermediate mold level with involute spline pathways extending in oppositely twisting helices from the central region toward opposite ends thereof and respective spline nuts secured to adjacent mold levels threadedly engaging the spline pathways to run therealong for converting linear motion into rotational motion and vice versa thereby controlling relative opening and closing rates of the adjacent mold levels relative to the intermediate mold levels therebetween. The cooling arrangement has an internal fluid passageway extending along the spline shaft into a region of the spline shaft received in the spline nuts. A fluid inlet communicates with and supplies fluid to the fluid passageway. A fluid outlet communicates with and discharges fluid from the fluid passageway. A fluid guide is provided for causing a fluid to flow along the fluid passageway to cool the region received in the spline nuts as the fluid passes from the inlet through the outlet.

    Abstract translation: 提供了一种用于多级堆叠模具的模具定心装置的冷却装置，其具有花键轴，所述花键轴具有轴颈到中间模具级的中心区域，其具有从中心区域朝向其相对端延伸的相反扭转螺旋的渐开线花键路径和相应的花键 螺母固定到相邻模具水平面上，螺纹地接合花键通道以沿着其运行以将线性运动转换成旋转运动，反之亦然，从而控制相邻模具水平相对于它们之间的中间模具水平的相对开启和关闭速度。 冷却装置具有沿着花键轴延伸到花键螺母中的花键轴的区域中的内部流体通道。 流体入口与流体通道连通并供应流体。 流体出口与流体通道连通并排出流体。 提供流体引导件，用于使流体沿着流体通道流动，以在流体从入口通过出口通过时冷却在花键螺母中容纳的区域。

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