公开(公告)号：US06211087B1

公开(公告)日：2001-04-03

申请号：US09106718

申请日：1998-06-29

Applicant: Calvin Gabriel ,  Milind Weling

Inventor： Calvin Gabriel ,  Milind Weling

IPC: H01L21302

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: A primary layer deposited over a secondary layer is planarized. A chemical mechanical polishing process is performed using a slurry which targets the primary layer. Then, chemical etching is performed using a chemical wet etchant which targets the secondary layer. The method is used, for example, when making connections to a lower layer through an insulating layer. Plug holes are formed through the insulating layer to the lower layer. Then the secondary layer is deposited. The secondary layer acts as a barrier layer or a glue layer.

Abstract translation: 沉积在次级层上的主层被平坦化。 使用针对主层的浆料进行化学机械抛光工艺。 然后，使用以二级层为目标的化学湿蚀刻剂进行化学蚀刻。 该方法例如在通过绝缘层连接到下层时使用。 插入孔穿过绝缘层到下层。 然后沉积二次层。 次级层用作阻挡层或胶层。

公开(公告)号：US08716135B1

公开(公告)日：2014-05-06

申请号：US12264139

申请日：2008-11-03

Applicant: Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

Inventor： Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/306

CPC classification number: H01L21/0338 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/30621

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

Abstract translation: 公开了使用双重图案化的半导体器件制造技术的方法。 根据本发明的各种实施例，提供了使用自对准双重图案化的半导体器件制造方法。 本发明的特定实施例允许使用两个光刻操作创建逻辑电路图案。 本发明的一个实施例采用自对准双重图案化来定义两组或更多组具有组之间的连接特征的平行线特征。 在这样的实施例中，使用两个光刻掩模来形成平行线特征的集合以及连接特征，而不需要额外的掩模层来形成连接。 在其他实施例中，除了连接之外的其他特征可以添加在相同的掩模层中。

公开(公告)号：US08440569B2

公开(公告)日：2013-05-14

申请号：US11952703

申请日：2007-12-07

Applicant: Milind Weling ,  Abdurrahman Sezginer

Inventor： Milind Weling ,  Abdurrahman Sezginer

IPC: H01L21/302

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.

Abstract translation: 公开了半导体器件制造方法。 示例性方法包括在半导体衬底上沉积第一图案的过程，其中第一图案限定宽而窄的空间; 在衬底上的第一图案上沉积间隔物材料; 蚀刻间隔物材料，使得间隔物材料从基底和第一图案的水平表面移除，但保持邻近由第一图案限定的宽空间的垂直表面，并保持在由第一图案限定的狭窄空间内; 并从衬底去除第一图案。 在一个实施例中，第一图案可以包括牺牲材料，其可以包括例如多晶硅材料。 沉积可以包括物理气相沉积，化学气相沉积，电化学沉积，分子束外延，原子层沉积或其它沉积技术。 根据另一个实施例，在相同掩模层中的间隔物材料中形成具有大于线的宽度的线和逻辑器件部件的特征。

公开(公告)号：US06569757B1

公开(公告)日：2003-05-27

申请号：US09429540

申请日：1999-10-28

Applicant: Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

Inventor： Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

IPC: H01L214763

CPC classification number: H01L23/5225 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  Y10T29/49123 ,  H01L2924/00

Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract translation: 提供了在电介质层中形成同轴互连线的方法。 该方法包括在电介质层中限定沟槽，然后在沟槽内形成屏蔽金属化层。 在形成屏蔽金属化层之后，在屏蔽金属化层内沉积保形氧化物层。 然后在保形氧化物层内形成中心导体。 一旦形成中心导体，就在中心导体上沉积填充氧化物层。 然后在填充氧化物层上形成帽金属化层，并与屏蔽金属化层接触。

公开(公告)号：US06387720B1

公开(公告)日：2002-05-14

申请号：US09461702

申请日：1999-12-14

Applicant: Michael Misheloff ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Milind Weling

Inventor： Michael Misheloff ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Milind Weling

IPC: H01L2100

CPC classification number: G02B6/13 ,  G02B6/42 ,  G02B6/43 ,  G02B2006/12176

Abstract: A waveguide structure and method of making a waveguide for communicating optical signals is provided. The waveguide structure is made using standard CMOS fabrication operations and is integrated on the same chip having digital CMOS circuitry. An example method of making the waveguide includes forming a contact through a dielectric layer down to a substrate and coating sidewalls of the contact with a first metallization coating. The contact is then filled with a dielectric material. A partial waveguide structure is formed over the first metallization coating and the dielectric material of the contact. The partial waveguide structure is defined by a waveguide dielectric structure and a second metallization coating that is defined over the waveguide dielectric structure. A third metallization coating is then formed to define spacers along sides of the partial waveguide structure, the first metallization coating, the second metallization coating. The third metallization coating is configured to complete the waveguide structure that is filled with the waveguide dielectric structure. Optical signals can then be propagated through the waveguide structure and can be interfaced with other CMOS digital circuitry.

Abstract translation: 提供了一种制造用于传送光信号的波导的波导结构和方法。 波导结构使用标准CMOS制造操作制成，并集成在具有数字CMOS电路的同一芯片上。 制造波导的示例性方法包括通过电介质层形成接触到下一个衬底并且将接触的侧壁涂覆到第一金属化涂层。 然后用电介质材料填充接触。 在第一金属化涂层和触点的电介质材料上形成部分波导结构。 部分波导结构由波导介电结构和在波导介电结构上限定的第二金属化涂层限定。 然后形成第三金属化涂层以沿着部分波导结构，第一金属化涂层，第二金属化涂层的侧面限定间隔物。 第三金属化涂层被配置成完成填充有波导介质结构的波导结构。 光信号然后可以通过波导结构传播，并且可以与其他CMOS数字电路接口。

公开(公告)号：US06242805B1

公开(公告)日：2001-06-05

申请号：US09436937

申请日：1999-11-08

Applicant: Milind Weling

Inventor： Milind Weling

IPC: H01L2148

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.

Abstract translation: 一种在铜化学机械抛光过程中使用抛光止挡膜控制凹陷的方法。 在一个实施例中，该方法包括几个步骤。 一步包括在设置在半导体晶片上的金属层上沉积抛光停止层。 另一步骤是将半导体晶片放置在化学机械抛光机的抛光垫上。 进一步的步骤涉及去除半导体晶片的金属层，并且还优先使用化学机械抛光工艺去除抛光停止层。 抛光停止层的优点是防止沟槽内的金属层的凹陷。 另一步骤是当从半导体晶片的期望区域去除金属层并且半导体晶片基本上是平面时停止化学机械抛光工艺。

公开(公告)号：US5420796A

公开(公告)日：1995-05-30

申请号：US173581

申请日：1993-12-23

Applicant: Milind Weling ,  Calvin T. Gabriel

Inventor： Milind Weling ,  Calvin T. Gabriel

IPC: G01Q60/00 ,  H01L21/66 ,  G06F15/46 ,  H01J3/14

CPC classification number: B82Y15/00 ,  H01L22/12 ,  Y10S977/854

Abstract: An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.

Abstract translation: 集成电路（IC）制造工艺涉及在半导体衬底上形成电子器件。 金属层沉积在其上，然后被图案化以使半导体器件互连。 电介质层沉积在金属层和衬底上。 回蚀电介质层以准备附加的金属和电介质层的沉积。 蚀刻的表面被原子力显微镜（AFM）扫描以收集表示晶片表面粗糙度的数据。 数据由计算机评估以产生至少一个表面粗糙度信号。 根据表面粗糙度信号的值，IC制造工艺继续下一步，采取补救措施，为随后的晶片调整IC制造工艺，或丢弃晶片。

公开(公告)号：US5378318A

公开(公告)日：1995-01-03

申请号：US893616

申请日：1992-06-05

Applicant: Milind Weling ,  Vivek Jain

Inventor： Milind Weling ,  Vivek Jain

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/76819

Abstract: A method for improved planarization of surface topographies encountered in semiconductor processing that involve the etch-back of exposed surfaces of an oxide of silicon and a spin-on-glass. The oxide of silicon is chosen to be oxygen-deficient and thus silicon-rich, with a spectroscopically-defined silicon richness coefficient CSR that is greater than 0, and preferably greater than 0.005. A fluorine-containing process gas such as CHF.sub.3 combined with one or more of CF.sub.4, C.sub.2 F.sub.6 and SF.sub.6 can be used in the etch chemistry. Sensitivity of the etch rate to certain parameters, such as the relative surface area of the exposed oxide of silicon and the fraction of fluorine present, is either reduced or eliminated. Improvement and better control of planarization is achieved by the process, resulting in a widening of the etch-back process window.

Abstract translation: 一种用于改善在半导体处理中遇到的表面形貌的平面化的方法，其涉及硅的氧化物和旋涂玻璃的暴露表面的回蚀。 硅的氧化物选择为缺氧的，因此富含硅，其光谱定义的硅富集系数CSR大于0，优选大于0.005。 在蚀刻化学中可以使用与CF4，C2F6和SF6中的一种或多种组合的含氟工艺气体，例如CHF 3。 蚀刻速率对某些参数（例如暴露的硅的氧化物的相对表面积和存在的氟的分数）的敏感度被降低或消除。 通过该过程实现了平坦化的改进和更好的控制，导致了回蚀加工窗口的扩大。

公开(公告)号：US08656321B1

公开(公告)日：2014-02-18

申请号：US13183749

申请日：2011-07-15

Applicant: Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

Inventor： Judy Huckabay ,  Milind Weling ,  Abdurrahman Sezginer

IPC: G06F17/50

CPC classification number: H01L21/0338 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/30621

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Abstract translation: 公开了使用双重图案化的半导体器件制造技术的方法。 根据本发明的各种实施例，提供了使用自对准双重图案化的半导体器件制造方法。 本发明的特定实施例允许使用两个光刻操作创建逻辑电路图案。 本发明的一个实施例采用自对准双重图案化来定义具有两个相邻组之间的连接特征的两组或多组平行线特征。 在这种实施例中，使用两个光刻掩模来形成平行线特征的集合以及连接特征，而不需要额外的掩模层来形成连接特征。 在其他实施例中，除了连接特征之外的其他特征可以添加在相同的掩模层中。

公开(公告)号：US07856613B1

公开(公告)日：2010-12-21

申请号：US12264853

申请日：2008-11-04

Applicant: Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

Inventor： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC classification number: H01L21/033 ,  G03F1/00

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract translation: 本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。 本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。