公开(公告)号：US20050097769A1

公开(公告)日：2005-05-12

申请号：US10668291

申请日：2003-09-24

申请人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/677 ,  F26B13/30

CPC分类号： H01L21/67781

摘要： A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

摘要翻译： 一个加载锁 用于晶片的负荷锁包括一个腔室，一个基座，一个伸缩轴和一个波纹管。 腔室具有多个壁和底面。 基座支撑盒并设置在腔室中。 伸缩轴具有顶端和底端。 顶端连接到基座，底端连接到底面作为基座的基准。 波纹管具有第一端和第二端。 第一端设置在基座上，第二端在可伸缩轴的底端被密封。 优选地，可伸缩轴被波纹管完全包围。

公开(公告)号：US06878615B2

公开(公告)日：2005-04-12

申请号：US09863224

申请日：2001-05-24

申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

摘要翻译： 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US20050054196A1

公开(公告)日：2005-03-10

申请号：US10657505

申请日：2003-09-08

申请人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8249

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

摘要： An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrate. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.

摘要翻译： 使用原子层沉积方法在衬底上沉积厚度约为50nm或更小的TiN或TiSiN膜。 四（二甲基氨基）钛（TDMAT），四（二乙基酰氨基）钛（TDEAT）或Ti {OCH（CH 3）2} 4）的钛前体避免了卤化钛前体的卤化物污染，并且比硝酸钛更安全 。 将钛前体的单层沉积在基底上之后，引入含氮反应物以形成TiN单层，随后进行第二次吹扫。 对于TiSiN，在TiN单层形成之后，将硅源气体进料到处理室中。 该过程重复几次以产生由填充接触孔的多个单层组成的复合层。 ALD方法具有成本效益，并且提供了比常规PECVD或CVD工艺更低的杂质水平和更好的阶梯覆盖的互连。

公开(公告)号：US6140241A

公开(公告)日：2000-10-31

申请号：US270591

申请日：1999-03-18

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Chen-Hua Yu

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the contact/vias are filled and additional copper is deposited over them at a high deposition rate. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.

摘要翻译： 描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。 该方法设计为通过在两个沉积阶段之间执行铜的电化学沉积，具有阶段之间的停留时间，以提供良好的覆盖和间隙填充能力以及高的生产量。 该方法使用含有添加的增白剂和矫直机的镀铜电解质。 第一次沉积以低电流密度进行，这提供了由高投掷功率引起的良好覆盖。 高长宽比的接触/通孔开口用相当厚度的均匀的高质量铜涂层覆盖。 在沉积期间，增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。 增亮剂的浓度，在电镀电流停止的短暂停留期间通过扩散在这些区域补充。 接下来，施加高电流密度，由此接触/通孔被填充，并且以高沉积速率在其上沉积额外的铜。 通过高电流密度步骤，当该方法应用于双镶嵌冶金的形成时，实现了最大的生产效率。

公开(公告)号：US20100230816A1

公开(公告)日：2010-09-16

申请号：US12787559

申请日：2010-05-26

申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

摘要翻译： 提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。 提供了一种半导体器件，包括衬底。 其中具有至少一个导电特征的电介质层覆盖在衬底上。 绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

公开(公告)号：US07597787B2

公开(公告)日：2009-10-06

申请号：US11072137

申请日：2005-03-04

申请人： Hung-Wen Su ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Ming-Hsing Tsai

IPC分类号： C25D3/06

CPC分类号： C25D17/001 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/76841

摘要： Methods and apparatuses for electrochemically depositing a metal layer onto a substrate. An electrochemical deposition apparatus comprises a substrate holder assembly including a substrate chuck and a relatively soft cathode contact ring. The cathode contact ring comprises an inner portion and an outer portion, wherein the inner portion directly contacts the substrate. An anode is disposed in an electrolyte container. A power supply connects the substrate holder assembly and the anode.

摘要翻译： 将金属层电化学沉积到基底上的方法和装置。 一种电化学沉积设备包括一个衬底保持器组件，该衬底保持器组件包括衬底卡盘和相对软的阴极接触环 阴极接触环包括内部部分和外部部分，其中内部部分直接接触基板。 阳极设置在电解质容器中。 电源连接衬底保持器组件和阳极。

公开(公告)号：US07026244B2

公开(公告)日：2006-04-11

申请号：US10637105

申请日：2003-08-08

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC分类号： H01C23/48

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

摘要翻译： 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US20060054508A1

公开(公告)日：2006-03-16

申请号：US10943744

申请日：2004-09-16

申请人： Ming-Wei Lin ,  Ming-Hsing Tsai

发明人： Ming-Wei Lin ,  Ming-Hsing Tsai

IPC分类号： C25D3/48 ,  C25D3/38 ,  C25D5/48

CPC分类号： H01L21/2885 ,  C25D3/02 ,  C25D3/38 ,  H01L21/7684

摘要： A new and improved method for electroplating a metal onto a substrate in such a manner as to render the metal essentially corrosion-resistant during subsequent substrate processing such as chemical mechanical polishing. The process involves incorporating nitrogen into the metal as the metal is electroplated onto the substrate. The process includes preparing the electroplating bath, placing a leveler chemical containing nitrogen in the prepared bath, circulating the leveler chemical throughout the bath and then electroplating the metal on the substrate. In a preferred embodiment, alkyl polyamide, alkyl amine, alkyl amine oxide or thiourea with molecular weight ranging from 100˜1,000,000 is used as the leveler chemical.

摘要翻译： 一种新的和改进的方法，用于将金属电镀到基底上，使得金属在随后的基底处理（例如化学机械抛光）中基本上具有耐腐蚀性。 该方法包括在将金属电镀到基底上时将氮掺入金属中。 该方法包括制备电镀浴，将准备好的浴中含有氮的矫正剂化学品放置在整个浴中，使整平剂化学品循环，然后将金属电镀在基底上。 在优选的实施方案中，使用分子量为100〜1,000,000的烷基聚酰胺，烷基胺，烷基氧化胺或硫脲作为矫光剂。

公开(公告)号：US06759750B2

公开(公告)日：2004-07-06

申请号：US10623910

申请日：2003-07-18

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai

IPC分类号： H01L2348

CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

摘要翻译： 一种用于在半导体制造中集成低K材料的方法。 该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。 图案化电介质层以形成柱状开口。 在半导体结构上沉积柱层; 从而用柱层填充柱状开口。 柱层被平坦化以形成嵌入在所述介电层中的柱。 柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。 在一个实施例中，在形成双镶嵌层间接触之前形成柱。 在另一个实施方案中，柱与层间接触同时形成。

公开(公告)号：US06620725B1

公开(公告)日：2003-09-16

申请号：US09395287

申请日：1999-09-13

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

摘要翻译： 描述用于在两个步骤中执行CMP的过程。 在沟槽已经形成并且用铜过度填充之后，在本发明的第一实施例中，最初使用硬焊盘去除大部分铜，直到达到一个点，其中凹陷效应将开始出现。 然后取代软焊盘，继续CMP直到除了沟槽中除去所有的铜。 在第二实施例中，使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。 如前所述，使用这种组合，直到达到点，其中凹陷效应将开始出现。 然后，除了沟槽之外，使用相对较低的压力结合相对高的转速直到除去所有的铜。 这两个实施例都导致刚好填充铜的沟槽，几乎没有凹陷效应，并且除了沟槽本身之外，所有痕迹的铜都被去除。