公开(公告)号：US06759750B2

公开(公告)日：2004-07-06

申请号：US10623910

申请日：2003-07-18

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai

IPC分类号： H01L2348

CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

摘要翻译： 一种用于在半导体制造中集成低K材料的方法。 该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。 图案化电介质层以形成柱状开口。 在半导体结构上沉积柱层; 从而用柱层填充柱状开口。 柱层被平坦化以形成嵌入在所述介电层中的柱。 柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。 在一个实施例中，在形成双镶嵌层间接触之前形成柱。 在另一个实施方案中，柱与层间接触同时形成。

公开(公告)号：US06620725B1

公开(公告)日：2003-09-16

申请号：US09395287

申请日：1999-09-13

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

摘要翻译： 描述用于在两个步骤中执行CMP的过程。 在沟槽已经形成并且用铜过度填充之后，在本发明的第一实施例中，最初使用硬焊盘去除大部分铜，直到达到一个点，其中凹陷效应将开始出现。 然后取代软焊盘，继续CMP直到除了沟槽中除去所有的铜。 在第二实施例中，使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。 如前所述，使用这种组合，直到达到点，其中凹陷效应将开始出现。 然后，除了沟槽之外，使用相对较低的压力结合相对高的转速直到除去所有的铜。 这两个实施例都导致刚好填充铜的沟槽，几乎没有凹陷效应，并且除了沟槽本身之外，所有痕迹的铜都被去除。

公开(公告)号：US06562725B2

公开(公告)日：2003-05-13

申请号：US09899420

申请日：2001-07-05

申请人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76829 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/7681 ,  H01L21/76834

摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.

摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。 第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。 通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

公开(公告)号：US06224737B1

公开(公告)日：2001-05-01

申请号：US09377540

申请日：1999-08-19

申请人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： C25D502

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/48 ,  C25D7/123 ,  H01L21/2885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.

摘要翻译： 提供具有形成在其中的沟槽的半导体结构。 半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。 电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。 将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。 由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。 然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。 然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。

公开(公告)号：US6133144A

公开(公告)日：2000-10-17

申请号：US368864

申请日：1999-08-06

申请人： Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/7681

摘要： An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of double etch stop or etch barrier layers. The key process step of this invention is special patterning of the etch stop or etch barrier layer. This is the advantage of this invention over Prior Art processes that need a continuous, thick stop layer that has a etching selectivity to silicon dioxide, SiO.sub.2 (increasing parasitic capacitance). However, in this invention a self aligned dual damascene process and structure is presented that is easier to process and has low parasitic capacitance. Repeating the self aligned dual damascene processing steps, constructs multilevel conducting structures. This process reduces processing time, reduces the cost of ownership, (compatible with low dielectric constant materials) and at the same time produces a product with superior lines and via contact structures (by use of special etch stop or etch barrier layer patterning), hence improving reliability.

摘要翻译： 已经开发了用于制造独特的互连导线和通孔接触结构的改进和新颖的工艺。 使用这种特殊的自对准双镶嵌工艺，形成了具有低寄生电容（低RC时间常数）的特殊互连导线和通孔触点。 本发明包括使用双蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是蚀刻停止或蚀刻阻挡层的特殊图案化。 这是本发明优于现有技术方法的优点，其需要具有对二氧化硅，SiO 2（增加寄生电容）的蚀刻选择性的连续的厚的停止层。 然而，在本发明中，提出了一种易于处理并具有低寄生电容的自对准双镶嵌工艺和结构。 重复自对准双镶嵌加工步骤，构建多层导电结构。 这个过程减少了处理时间，降低了所有权成本（与低介电常数材料兼容），同时产生了具有优异线条和通孔接触结构的产品（通过使用特殊的蚀刻阻挡层或蚀刻阻挡层图案），因此 提高可靠性。

公开(公告)号：US07312531B2

公开(公告)日：2007-12-25

申请号：US11261200

申请日：2005-10-28

申请人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

发明人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/53276 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

公开(公告)号：US20070181434A1

公开(公告)日：2007-08-09

申请号：US11783245

申请日：2007-04-06

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： C25D5/34 ,  H01L21/44 ,  C25D3/38

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

摘要翻译： 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US20050170648A1

公开(公告)日：2005-08-04

申请号：US11056758

申请日：2005-02-11

申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

公开(公告)号：US07354856B2

公开(公告)日：2008-04-08

申请号：US11071104

申请日：2005-03-04

申请人： Ming-Shih Yeh ,  Ming-Hsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Shih Yeh ,  Ming-Hsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/44

CPC分类号： H01L21/76804 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/76808 ,  Y10S438/978

摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.

摘要翻译： 提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。 在一个实施例中，具有导电层的衬底形成在第一绝缘层中。 在导电层上形成保护层。 在保护层和第一绝缘层上方形成蚀刻停止层。 在蚀刻停止层上形成第二绝缘层。 第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。 将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。 通孔塞至少部分地填充在第一开口中。 在第二绝缘层上方形成抗反射涂层（ARC）层。 第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。 第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

公开(公告)号：US20070287294A1

公开(公告)日：2007-12-13

申请号：US11448713

申请日：2006-06-08

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/321 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859

摘要： Methods for fabricating interconnect structures are provided. An exemplary method for fabricating an interconnect comprises providing a substrate with a first dielectric layer thereon. At least one conductive feature is formed in the first dielectric layer. A conductive cap is selectively formed to overlie the conductive feature. A surface treatment is performed on the first dielectric layer and the conductive cap. A second dielectric layer is then formed to overlie the first dielectric layer.

摘要翻译： 提供制造互连结构的方法。 用于制造互连的示例性方法包括在其上提供其上具有第一介电层的衬底。 在第一介电层中形成至少一个导电特征。 选择性地形成导电盖以覆盖导电特征。 在第一电介质层和导电盖上进行表面处理。 然后形成第二电介质层以覆盖第一电介质层。