公开(公告)号：US5489500A

公开(公告)日：1996-02-06

申请号：US97601

申请日：1993-07-27

Applicant: John Andrejack ,  Natalie B. Feilchenfeld ,  David B. Stone ,  Paul G. Wilkin ,  Michael Wozniak

Inventor： John Andrejack ,  Natalie B. Feilchenfeld ,  David B. Stone ,  Paul G. Wilkin ,  Michael Wozniak

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  G03F7/26

CPC classification number: H05K3/4635 ,  H05K3/462 ,  H05K3/4641 ,  H05K1/0393 ,  H05K2201/09318 ,  H05K2201/09536 ,  H05K3/0047 ,  H05K3/4623 ,  H05K3/4691

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. The individual circuitized flexible strips are discrete subassemblies. These subassemblies are laminates of at least one internal power core, and at least one signal core, with a layer of dielectric between.

Abstract translation: 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个电路化的柔性条是离散的子组件。 这些子组件是至少一个内部功率核心的层压板，以及至少一个信号芯，其间具有介电层。

公开(公告)号：US4883744A

公开(公告)日：1989-11-28

申请号：US196641

申请日：1988-05-17

Applicant: Natalie B. Feilchenfeld ,  Stephen J. Fuerniss ,  John J. Glenning ,  Walter P. Pawlowski ,  Giana M. Phelan ,  Paul G. Rickerl

Inventor： Natalie B. Feilchenfeld ,  Stephen J. Fuerniss ,  John J. Glenning ,  Walter P. Pawlowski ,  Giana M. Phelan ,  Paul G. Rickerl

IPC: H05K3/06 ,  G03F7/038 ,  G03F7/16 ,  G03F7/32 ,  H01L21/768 ,  H01L23/522 ,  H05K1/03 ,  H05K3/46

CPC classification number: G03F7/0387 ,  G03F7/168 ,  G03F7/32

Abstract: A polyimide pattern is formed on a substrate by providing a layer of photosensitive polyimide precursor containing the polyimide precursor and a compound having a photosensitive group on the substrate and prebaking the layer. The layer is then exposed imagewise to actinic radiation through a photomask to form an exposed image pattern of the polyimide precursor in the layer. The unexposed areas of the layer are removed using a liquid developer and the exposed image pattern is cured by heating. In one aspect of the present invention, the prebaking step employs a judicious selection of times and temperature to eliminate the problem of formation of a white residue that occurs from using prior art prebake procedures. In another aspect of the present invention, a particular liquid developer composition is employed to facilitate the formation of sloped vias in the polyimide. In another aspect of the present invention, a particular range of exposure wavelength(s) is employed to obtain smooth walled vias.

公开(公告)号：US20130175656A1

公开(公告)日：2013-07-11

申请号：US13345881

申请日：2012-01-09

Applicant: Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

Inventor： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L29/866 ,  H01L21/76 ,  H01L21/76283 ,  H01L27/0255 ,  H01L29/66106

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract translation: 公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可缩放反向偏压击穿电压（Vb）。 具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。 然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。 为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。 还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。

公开(公告)号：US20120319233A1

公开(公告)日：2012-12-20

申请号：US13472044

申请日：2012-05-15

Applicant: Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

Inventor： Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

IPC: H01L29/73

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract translation: 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

公开(公告)号：US07892910B2

公开(公告)日：2011-02-22

申请号：US11680163

申请日：2007-02-28

Applicant: Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

Inventor： Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

IPC: H01L21/8238

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract translation: 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

公开(公告)号：US20080203490A1

公开(公告)日：2008-08-28

申请号：US11680163

申请日：2007-02-28

Applicant: Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

Inventor： Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

IPC: H01L29/73 ,  H01L21/8238

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract translation: 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

公开(公告)号：US06809024B1

公开(公告)日：2004-10-26

申请号：US10249821

申请日：2003-05-09

Applicant: James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

Inventor： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

IPC: H01L2972

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

公开(公告)号：US08525293B2

公开(公告)日：2013-09-03

申请号：US13472044

申请日：2012-05-15

Applicant: Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

Inventor： Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

IPC: H01L29/73

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract translation: 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

公开(公告)号：US08227849B2

公开(公告)日：2012-07-24

申请号：US12706834

申请日：2010-02-17

Applicant: Ebenezer E Eshun ,  Ronald J Bolam ,  Douglas D Coolbaugh ,  Keith E Downes ,  Natalie B Feilchenfeld ,  Zhong-Xiang He

Inventor： Ebenezer E Eshun ,  Ronald J Bolam ,  Douglas D Coolbaugh ,  Keith E Downes ,  Natalie B Feilchenfeld ,  Zhong-Xiang He

IPC: H01L29/92

CPC classification number: H01L28/60

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract translation: 本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。 本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

公开(公告)号：US20120126319A1

公开(公告)日：2012-05-24

申请号：US13364663

申请日：2012-02-02

Applicant: Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

Inventor： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Abstract translation: 形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。 因此，漏极区域与栅电极的边缘自对准。 一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。 在形成漏极区域之后，一次性结构被去除。 漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。