公开(公告)号：US07772098B2

公开(公告)日：2010-08-10

申请号：US12593141

申请日：2008-03-26

申请人： Osamu Kusumoto ,  Chiaki Kudou ,  Kunimasa Takahashi

发明人： Osamu Kusumoto ,  Chiaki Kudou ,  Kunimasa Takahashi

IPC分类号： H01L21/425 ,  H01L21/265 ,  B05C13/00 ,  B05C13/02 ,  B05C21/00

CPC分类号： H01L29/7802 ,  H01J2237/2001 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811

摘要： On one face of a semiconductor wafer 1 having a first face (principal face) 1a and a second face (rear face) 1b, a protection film 2 is formed. When allowing the semiconductor wafer 1 to be attracted onto an attracting face of an electrostatic chuck 6 which is heated to 400° C. or more, the semiconductor wafer 1 is attracted onto the attracting face via the protection film 2. While heating the semiconductor wafer 1 to 400° C. or more, an ion implantation is performed for the face of the semiconductor wafer 1 on which the protection film 2 is not formed. Thereafter, the protection film 2 is removed from the semiconductor wafer 1.

摘要翻译： 在具有第一面（主面）1a和第二面（背面）1b的半导体晶片1的一个面上形成保护膜2。 当允许半导体晶片1被吸引到被加热到400℃或更高的静电卡盘6的吸引面上时，半导体晶片1经由保护膜2被吸引到吸引面上。在加热半导体晶片 1〜400℃以上时，对未形成保护膜2的半导体晶片1的面进行离子注入。 此后，保护膜2从半导体晶片1去除。

公开(公告)号：US20080265260A1

公开(公告)日：2008-10-30

申请号：US11570269

申请日：2005-06-10

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Koichi Hashimoto

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Koichi Hashimoto

IPC分类号： H01L29/24

CPC分类号： H01L29/7828 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365

摘要： A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path 20 of the power device includes: a JFET (junction) region 2, a drift region 3, and a substrate 4, which have ON resistances exhibiting a positive temperature dependence; and a channel region 1, which has an ON resistance exhibiting a negative temperature dependence. A temperature-induced change in the ON resistance of the entire power device is derived by allowing a temperature-induced change ΔRp in the ON resistance in the JFET (junction) region 2, the drift region 3, and the substrate 4, which have ON resistances exhibiting a positive temperature dependence, and a temperature-induced change ΔRn in the ON resistance in the channel region 1, which has an ON resistance exhibiting a negative temperature dependence, to cancel out each other. With respect to an ON resistance of the entire power device at −30° C., a ratio of change in the ON resistance of the entire power device when a temperature of the power device is varied from −30° C. to 100° C. is 50% or less.

摘要翻译： 通过使用宽带隙半导体形成具有晶体管结构的功率器件。 功率器件的电流通路20包括：具有呈现正温度依赖性的导通电阻的JFET（结）区域2，漂移区域3和衬底4; 以及具有呈现负温度依赖性的导通电阻的沟道区域1。 通过使JFET（结）区域2，漂移区域3中的导通电阻中的温度感应变化ΔR

<！ - SIPO - >于高电平，导致整个功率器件的导通电阻的温度引起的变化， 并且具有呈现正温度依赖性的导通电阻的基板4和沟道区域1中的导通电阻中的温度感应变化ΔR ，其具有呈现负温度依赖性的导通电阻 ，取消对方。 关于整个功率器件在-30℃的导通电阻，当功率器件的温度从-30℃变化到100℃时，整个功率器件的导通电阻的变化率 50％以下。

公开(公告)号：US20070158778A1

公开(公告)日：2007-07-12

申请号：US10588960

申请日：2005-08-26

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Koichi Hashimoto

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Koichi Hashimoto

IPC分类号： H01L23/58

CPC分类号： H02M7/538 ,  H01L21/8213 ,  H01L21/8252 ,  H01L24/73 ,  H01L27/0605 ,  H01L27/0727 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M7/003 ,  H03K17/063 ,  H03K17/6871 ,  Y02B70/1483 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device section (28a,28b) which intervenes between the first electrode and the signal output electrode and is brought into or out of conduction according to a signal inputted to the control electrode and a resistor device section (Ra,Rb) which intervenes between the signal output electrode and the second electrode, the first semiconductor region comprising a wide bandgap semiconductor; and a diode (23) having a cathode-side electrode, an anode-side electrode, and a second semiconductor region comprising a wide bandgap semiconductor.

摘要翻译： 根据本发明的半导体器件包括：具有第一和第二电极的两个电平移位开关（28A和28B），控制电极，信号输出电极和形成晶体管器件部分（28a， 28b），其介于所述第一电极和所述信号输出电极之间，并且根据输入到所述控制电极的信号和介于所述信号输出电极和所述信号输出电极之间的电阻器部分（Ra，Rb）而导通或导通; 第二电极，第一半导体区域包括宽带隙半导体; 以及具有阴极侧电极，阳极侧电极和包括宽带隙半导体的第二半导体区域的二极管（23）。

公开(公告)号：US20060220027A1

公开(公告)日：2006-10-05

申请号：US10553845

申请日：2005-01-28

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

IPC分类号： H01L31/0312 ,  H01L21/265

CPC分类号： H01L21/046

摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

摘要翻译： 一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5） 在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火 碳层（5）。

公开(公告)号：US06989553B2

公开(公告)日：2006-01-24

申请号：US10625256

申请日：2003-07-23

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

IPC分类号： H01L31/0312

CPC分类号： H01L29/155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/812 ,  H01L29/872

摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

摘要翻译： 有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。 由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。 在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值 通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

公开(公告)号：US20050173739A1

公开(公告)日：2005-08-11

申请号：US10494705

申请日：2003-07-09

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Masao Uchida

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Masao Uchida

IPC分类号： H01L21/28 ,  H01L21/04 ,  H01L21/336 ,  H01L21/338 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/095 ,  H01L29/12 ,  H01L29/24 ,  H01L29/36 ,  H01L29/45 ,  H01L29/47 ,  H01L29/772 ,  H01L29/78 ,  H01L29/812 ,  H01L29/872 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7813 ,  H01L21/0485 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931

摘要： An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

摘要翻译： 累积模式MISFET包括：在SiC衬底101上外延生长的高电阻SiC层102; 井区域103; 具有形成在阱区域103的表面区域上的多个δ-掺杂层的累积沟道层104; 接触区域105; 栅极绝缘膜108; 和栅电极110。 累积通道层104具有这样的结构，其中未掺杂层104b和δ-掺杂层104a允许载流子在量子效应下向未掺杂层104b的扩展移动交替堆叠。 提供源电极111，其进入累积沟道层104和接触区域105以与接触区域105直接接触。 不需要通过离子注入形成源极区域，导致制造成本的降低。

公开(公告)号：US06900483B2

公开(公告)日：2005-05-31

申请号：US10162503

申请日：2002-06-04

申请人： Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Ryoko Miyanaga ,  Kenya Yamashita

发明人： Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Ryoko Miyanaga ,  Kenya Yamashita

IPC分类号： H01L21/329 ,  H01L29/24 ,  H01L29/872 ,  H01L29/80

CPC分类号： H01L29/66143 ,  H01L29/1608 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

摘要翻译： 肖特基二极管包括由4H-SiC制成的半导体衬底，外延生长的4H-SiC层，离子注入层，肖特基电极，欧姆电极和由热氧化膜制成的绝缘层。 肖特基电极和绝缘层彼此不接触，其间设置有间隙，由此不发生改变的层。 因此，可以抑制泄漏电流的发生。

公开(公告)号：US20050077569A1

公开(公告)日：2005-04-14

申请号：US10956078

申请日：2004-10-04

申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L29/15

CPC分类号： H01L29/518 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/7828

摘要： A gate insulating film which is an oxide layer mainly made of SiO2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100° C. and lower than 1250° C., whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.

摘要翻译： 通过热氧化在碳化硅衬底上形成作为主要由SiO 2形成的氧化物层的栅极绝缘膜，然后将所得结构在室内的惰性气体气氛中退火。 然后，将碳化硅 - 氧化物层叠体置于具有真空泵的室内，在高于1100℃且低于1250℃的高温下暴露于减压NO气体气氛中，由此氮气扩散 在栅极绝缘膜上。 结果，获得了包含氧化物层的V族元素的栅绝缘膜，其下部包括高氮浓度区域，并且其相对介电常数为3.0或更高。 含V族元素的氧化物层和碳化硅层之间的界面区域的界面态密度降低。

公开(公告)号：US06654604B2

公开(公告)日：2003-11-25

申请号：US09989270

申请日：2001-11-20

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

IPC分类号： H04Q720

CPC分类号： H03F3/601 ,  H01L21/8213 ,  H01L27/0605 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/812 ,  H01L29/872 ,  H03D7/125 ,  H03F2200/294

摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.

摘要翻译： 用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。 第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。 第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。 由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

公开(公告)号：US5835312A

公开(公告)日：1998-11-10

申请号：US743360

申请日：1996-11-04

申请人： Akio Kuroe ,  Akio Murata ,  Kazuo Yokoyama ,  Osamu Kusumoto

发明人： Akio Kuroe ,  Akio Murata ,  Kazuo Yokoyama ,  Osamu Kusumoto

IPC分类号： G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B5/127 ,  G11B5/31 ,  G11B5/33 ,  G11B5/39 ,  G11B5/48 ,  G11B5/58 ,  G11B9/00 ,  G11B9/04

CPC分类号： B82Y10/00 ,  G11B5/00 ,  G11B5/012 ,  G11B5/1278 ,  G11B5/3106 ,  G11B5/3113 ,  G11B5/3116 ,  G11B5/313 ,  G11B5/3163 ,  G11B5/33 ,  G11B5/332 ,  G11B5/4826 ,  G11B5/484 ,  G11B5/58 ,  G11B2005/0005 ,  G11B9/14 ,  G11B9/1418

摘要： The present invention relates to a magnetic head for recording and reproducing signals from a magnetic recording medium, wherein the magnetic head comprises a stylus having a pair of electrodes, a conductive multilayer film having a staircase-shaped section, and a magnetic body formed on the multilayer film. The magnetic head further comprises an excitation conductive thin film disposed so as to surround the stylus, a magnetic yoke forming a closed magnetic loop together with a magnetic recording medium and the stylus, and an anti-abrasive film formed on the magnetic yoke so as to oppose the recording medium. During recording, a signal current is supplied to the excitation conductive thin film to generate a recording magnetic field from the end of the stylus. During reproduction, a high-frequency voltage is applied across the electrodes, and a magnetic impedance change of the stylus, caused by a signal magnetism on the recording medium, is detected. The relative position of the magnetic head to the recording medium is controlled by deflecting a cantilever according to a capacitance between the magnetic head and the recording medium. Accordingly, the magnetic head of the present invention is capable of remarkably enhancing recording densities and data transfer rates.

摘要翻译： 本发明涉及一种用于记录和再现来自磁记录介质的信号的磁头，其中磁头包括具有一对电极的触针，具有阶梯形截面的导电多层膜和形成在其上的磁体 多层膜。 磁头还包括设置成围绕触针的激励导电薄膜，与磁记录介质和触针一起形成闭合磁环的磁轭，以及形成在磁轭上的抗磨膜，以便 对着记录介质。 在记录期间，向激励导电薄膜提供信号电流以从触针的端部产生记录磁场。 在再现期间，在电极之间施加高频电压，并且检测由记录介质上的信号磁性引起的触针的磁阻抗变化。 通过根据磁头和记录介质之间的电容使悬臂偏转来控制磁头与记录介质的相对位置。 因此，本发明的磁头能够显着提高记录密度和数据传送速率。