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公开(公告)号：US06614705B2
公开(公告)日：2003-09-02
申请号：US09819488
申请日：2001-03-28
IPC分类号： G11C800
CPC分类号： G11C5/145 , G05F3/205 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译： 用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。 升压电路中的晶体管完全切换，消除了Vtn通过晶体管降低升压电压。 升压电容器由Vdd充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。
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公开(公告)号：USRE37641E1
公开(公告)日：2002-04-09
申请号：US08853507
申请日：1997-05-08
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4091 , G11C11/4094
摘要： Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense noes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.
摘要翻译： 用于控制位线感测的装置和方法，其有助于随时分布的位线充电电流的分布，并且有助于将感测模式快速升高到完全逻辑电平。 一个实施例包括多个位存储电容器，用于接收存储在其中一个电容器上的电荷的折叠位线，具有位线电容，读出放大器具有用于感测跨感测节点的电压差的一对感测节点， 连接到位线的装置和感测节点，用于使感测节点与位线不完全隔离，由此电流可以泄漏，用于使读出放大器和禁用隔离装置的装置，从而消除读出放大器和位之间的隔离 线路，由此使通过感测放大器的电流到感测位置能够通过隔离装置将位线电容充电到预定的逻辑电压电平。
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公开(公告)号：US5844916A
公开(公告)日：1998-12-01
申请号：US429544
申请日：1995-04-27
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G01R31/3183 , G06F11/273 , G06F11/00
CPC分类号： G06F11/2635 , G01R31/3183
摘要： A method of testing an integrated circuit chip comprised of applying to and storing a first test pattern of data on the chip, applying a second test pattern of data to the chip which corresponds to the first test pattern, comparing the stored test pattern with the second test pattern on the chip, and indicating a test fault on a test pad in the event at least one bit of the first and second test pattern differ from each other.
摘要翻译： 一种测试集成电路芯片的方法，包括在芯片上应用和存储数据的第一测试模式，将对应于第一测试模式的数据的第二测试模式应用于芯片，将存储的测试模式与第二测试模式进行比较 在芯片上的测试图案，并且在第一和第二测试图案的至少一位彼此不同的情况下，在测试平台上指示测试故障。
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公开(公告)号：US5703508A
公开(公告)日：1997-12-30
申请号：US749408
申请日：1996-11-15
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： H03K19/00 , H03K19/017 , H03K3/037
CPC分类号： H03K19/01707 , H03K19/0027
摘要： A method of repeating a pulse signal comprised of outputting a signal at a first voltage level upon a first rising edge of the pulse signal exceeding a low threshold, then raising the threshold and outputting the signal at another voltage level upon a second trailing edge of the pulse signal dropping below the raised threshold. An improved VLSI circuit has at least one conductive track containing distributed parasitic elements, the track being divided into two or more separate segments, a repeater connecting each of the segments, and apparatus for modulating the threshold of the repeater prior to and/or during the interval of a pulse carried by the track.
摘要翻译： 一种重复脉冲信号的方法，该脉冲信号包括在脉冲信号的第一上升沿超过低阈值时以第一电压电平输出信号，然后升高该阈值并在该第二电压电平的第二后沿将该信号输出 脉冲信号降低到提升阈值以下。 改进的VLSI电路具有至少一个包含分布式寄生元件的导电轨道，该轨道被分成两个或更多个分开的段，连接每个段的中继器，以及用于在之前和/或期间调制中继器的阈值的装置 轨道携带的脉冲间隔。
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公开(公告)号：US5042012A
公开(公告)日：1991-08-20
申请号：US497267
申请日：1990-03-22
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G11C7/10 , G11C11/4096
CPC分类号： G11C7/1051 , G11C11/4096
摘要： A dynamic random access memory having a serial access data port. A plurality of complimentary bitline pairs are provided for receiving data signals from a plurality of memory cells, and a plurality of latches are connected to respective ones of the bitline pairs for periodically sensing and restoring the data signals in the memory cells. Predetermined ones of the latches are connected together via a plurality of isolation transfer gates which are enabled according to a predetermined timing sequence for unidirectionally shifting the data signals therebetween according to a master-slave action.
摘要翻译： 具有串行访问数据端口的动态随机存取存储器。 多个互补位线对被提供用于从多个存储单元接收数据信号，并且多个锁存器连接到相应的位线对，用于周期性地检测和恢复存储器单元中的数据信号。 预定的锁存器通过多个隔离传递门连接在一起，这些隔离传输门根据预定的时序顺序被使能，以便根据主 - 从动作在其间单向移位数据信号。
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公开(公告)号：US4786830A
公开(公告)日：1988-11-22
申请号：US65199
申请日：1987-06-22
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： H03K3/353 , H03K3/3565 , H03K19/017 , H03K19/0185 , H03K19/0948 , H03K17/30
CPC分类号： H03K19/01721 , H03K19/018521 , H03K3/3565
摘要： A TTL to CMOS-input buffer has minimal sensitivity of threshold level variation with changes in device parameters. In particular, the design is insensitive to P-channel characteristics over very wide ranges of transistor threshold voltages and gain parameter spreads.
摘要翻译： TTL到CMOS输入缓冲器具有最小的灵敏度阈值电平变化与器件参数的变化。 特别地，在非常宽的晶体管阈值电压和增益参数扩展范围内，该设计对P沟道特性不敏感。
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公开(公告)号：US06657919B2
公开(公告)日：2003-12-02
申请号：US10348062
申请日：2003-01-17
IPC分类号： G11C800
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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公开(公告)号：US06205083B1
公开(公告)日：2001-03-20
申请号：US09392088
申请日：1999-09-08
IPC分类号： G11C800
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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公开(公告)号：US5796673A
公开(公告)日：1998-08-18
申请号：US319042
申请日：1994-10-06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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公开(公告)号：US4980862A
公开(公告)日：1990-12-25
申请号：US268590
申请日：1988-11-08
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.
摘要翻译： 具有降低的共享电源电压的折叠位线动态RAM电路，包括用于在RAM电路的连续有效周期期间将全逻辑高电平和低电源电压施加到相应位线的电路，以及用于在连续预充电周期期间将位电源施加减小的电源电压的电路。 通过在预充电循环期间对位线施加减小的电源电压，RAM电路的单元存取晶体管和读出放大器的电压降低。 在活动周期开始时分享驻留在位线一半的电荷所需的时间也减少了。
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