公开(公告)号：US07186623B2

公开(公告)日：2007-03-06

申请号：US10625733

申请日：2003-07-24

申请人： Tetsuya Nitta ,  Tomohide Terashima

发明人： Tetsuya Nitta ,  Tomohide Terashima

IPC分类号： H01L21/331

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

公开(公告)号：US20050282375A1

公开(公告)日：2005-12-22

申请号：US11152790

申请日：2005-06-15

申请人： Tetsuya Nitta ,  Takayuki Igarashi

发明人： Tetsuya Nitta ,  Takayuki Igarashi

IPC分类号： H01L21/265 ,  H01L21/4763 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/78 ,  H01L29/788 ,  H01L29/861

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7317 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/8611

摘要： An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

摘要翻译： 在半导体衬底上形成有一个BOX层的N层。 在N层中，形成沟槽隔离区域以包围N层以成为元件形成区域。 沟槽隔离区形成为从N层的表面到达BOX层。 在沟槽隔离区域和N层之间，形成P型扩散区域10a。 连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。 在N层的元件形成区域中，形成规定的半导体元件。 因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。

公开(公告)号：US06949798B2

公开(公告)日：2005-09-27

申请号：US10416287

申请日：2002-01-28

申请人： Tetsuya Nitta ,  Tadaharu Minato

发明人： Tetsuya Nitta ,  Tadaharu Minato

IPC分类号： H01L21/265 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/861

摘要： The semiconductor device of the present invention has a repeat structure of repeated unit structures in a semiconductor substrate (1), each unit structure having an n type diffusion region (3) and a p type diffusion region (4) in contact with each other to form a pn junction sandwiched between trenches (1a). An impurity amount in the n type diffusion region (3) and an impurity amount in the p type diffusion region (4) in the unit structure are set unequal (or different). Thus, in the semiconductor device having the trenches (1a), favorable breakdown voltage and avalanche breakdown tolerance can be ensured at the same time.

摘要翻译： 本发明的半导体器件具有在半导体衬底（1）中重复的单位结构的重复结构，每个单位结构具有n型扩散区（3）和ap型扩散区（4）彼此接触以形成 夹在沟槽（1a）之间的pn结。 单元结构中的n型扩散区域（3）中的杂质量和p型扩散区域（4）中的杂质量被设定为不等（或不同）。 因此，在具有沟槽（1a）的半导体器件中，可以同时确保有利的击穿电压和雪崩击穿公差。

公开(公告)号：US20150014744A1

公开(公告)日：2015-01-15

申请号：US14378720

申请日：2012-02-16

申请人： Mikio Tsujiuchi ,  Tetsuya Nitta

发明人： Mikio Tsujiuchi ,  Tetsuya Nitta

IPC分类号： H01L29/739 ,  H01L29/417

CPC分类号： H01L29/7393 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708

摘要： In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.

摘要翻译： 在电流优先的IGBT中，集电极导电层通过多个触点与包含在集电极区域中的集电极有源区域连接。 集电极导电层与一个集电极有源区连接的触点数量大于发射极导体层与包括在基极区域中的一个基极活性区域连接的触点数。

公开(公告)号：US08710619B2

公开(公告)日：2014-04-29

申请号：US13208273

申请日：2011-08-11

申请人： Tatsuya Kawamata ,  Atsushi Tachigami ,  Kazuya Horie ,  Tatsuya Shiromoto ,  Tetsuya Nitta ,  Hironori Shimizu

发明人： Tatsuya Kawamata ,  Atsushi Tachigami ,  Kazuya Horie ,  Tatsuya Shiromoto ,  Tetsuya Nitta ,  Hironori Shimizu

IPC分类号： H01L21/70

CPC分类号： H01L21/76283 ,  H01L21/3065 ,  H01L21/76232 ,  H01L29/7833

摘要： To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 μm. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.

摘要翻译： 为了在元件隔离的元件区域的外围设置在SOI衬底上形成的SOI衬底的半导体层的半导体器件中，能够防止因元件隔离引起的可靠性劣化的技术。 通过将深沟槽构造沟槽隔离的上部的沟槽宽度设定为小于1.2，可以防止从绝缘膜的上表面填充具有绝缘膜的深沟槽形成的中空部的外观 μm。 可以通过在深沟槽的上部形成连接到深沟槽的上部的LOCOS绝缘膜来防止由于深沟槽的上部的沟槽宽度的减小而可能发生的相邻元件区域之间的击穿电压的降低 绝缘膜填充在深沟槽中。

公开(公告)号：US08569839B2

公开(公告)日：2013-10-29

申请号：US13010417

申请日：2011-01-20

申请人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

发明人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

IPC分类号： H01L21/8238 ,  H01L21/70

CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

摘要翻译： 提供可以使用简单的工艺制造而不确保高嵌入性的半导体器件; 以及该装置的制造方法。 在根据本发明的半导体器件的制造方法中，首先准备具有通过堆叠支撑衬底，埋入绝缘膜和半导体层获得的构造的半导体衬底。 然后，在半导体层的主表面上完成具有导电部分的元件。 形成了在平面图中包围元件并从半导体层的主表面到达掩埋绝缘膜的沟槽。 在元件上和沟槽中形成第一绝缘膜（层间绝缘膜）以覆盖元件并分别在沟槽中形成气隙。 然后，在第一绝缘膜中形成到达元件的导电部分的接触孔。

公开(公告)号：US20120139087A1

公开(公告)日：2012-06-07

申请号：US13305418

申请日：2011-11-28

申请人： Yasuki YOSHIHISA ,  Tetsuya NITTA

发明人： Yasuki YOSHIHISA ,  Tetsuya NITTA

IPC分类号： H01L29/02

CPC分类号： H01L27/088 ,  H01L21/823481 ,  H01L27/0248

摘要： The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.

摘要翻译： 半导体器件包括：半导体衬底; 一对注射元件; 主动屏障结构; 和p型接地区域。 半导体衬底具有形成在其中的主表面和p型区域。 主动屏障结构布置在主表面上夹在该对注入元件之间的区域中。 所述p型接地区域是形成为比所述一对注入元件和所述有源势垒结构更接近所述主面的端侧的接地电位适用区域，所述区域绕着所述一对注入元件之间夹在所述主体 表面，并且其电耦合到p型区域。 p型接地区域被夹在一对注入元件之间的区域相邻的区域划分。

公开(公告)号：US08030730B2

公开(公告)日：2011-10-04

申请号：US12401889

申请日：2009-03-11

申请人： Tetsuya Nitta ,  Takayuki Igarashi

发明人： Tetsuya Nitta ,  Takayuki Igarashi

IPC分类号： H01L29/00

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7317 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/8611

摘要： An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N-layer. Between trench isolation region and the N-layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N-layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

摘要翻译： 在半导体衬底上形成N层，插入BOX层。 在N层中，形成沟槽隔离区以包围作为元件形成区域的N层。 沟槽隔离区形成为从N层的表面到达BOX层。 在沟槽隔离区域和N层之间形成P型扩散区域10a。 连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。 在N层的元件形成区域中，形成规定的半导体元件。 因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。

公开(公告)号：US07942080B2

公开(公告)日：2011-05-17

申请号：US12068933

申请日：2008-02-13

申请人： Tetsuya Nitta

发明人： Tetsuya Nitta

IPC分类号： B23Q16/10

CPC分类号： B23Q1/28 ,  B23Q16/102 ,  Y10T74/14 ,  Y10T74/1494

摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

摘要翻译： 分度台组件包括旋转台，沿旋转台的旋转轴线的方向与旋转台分离的框架，用于通过沿旋转轴线移动旋转台来使旋转台与框架接触的夹紧装置 设置在所述转台和所述框架之间的第一轴承以及设置在所述第一轴承与所述旋转台和所述框架中的一个之间的推动装置，并且至少在所述旋转台和所述框架中将所述第一轴承压靠在所述旋转台和所述框架中的另一个上时 旋转台旋转。

公开(公告)号：US20100181640A1

公开(公告)日：2010-07-22

申请号：US12690714

申请日：2010-01-20

申请人： Tatsuya SHIROMOTO ,  Tetsuya Nitta ,  Shigeo Tokumitsu

发明人： Tatsuya SHIROMOTO ,  Tetsuya Nitta ,  Shigeo Tokumitsu

IPC分类号： H01L29/06

CPC分类号： H01L21/76264

摘要： Provided is a semiconductor device about which the reliability thereof is certainly kept even when a void is generated in a buried film in its trench. A rectangular element formation region is formed in a silicon layer. A trench having a predetermined width is formed to surround the element formation region. A first TEOS film and a second TEOS film are buried in the trench. A protecting film is formed at an L-shaped intersection region of the trench.

摘要翻译： 提供一种半导体器件，即使在其沟槽中的掩埋膜中产生空隙时，其可靠性肯定保持不变。 在硅层中形成矩形元件形成区域。 形成具有预定宽度的沟槽以包围元件形成区域。 第一TEOS膜和第二TEOS膜被埋在沟槽中。 保护膜形成在沟槽的L形交叉区域。