公开(公告)号：US20110273654A1

公开(公告)日：2011-11-10

申请号：US12814503

申请日：2010-06-14

申请人： Tsan-Chun Wang ,  Yu-Cheng Chen

发明人： Tsan-Chun Wang ,  Yu-Cheng Chen

IPC分类号： G02F1/1343

CPC分类号： G02F1/1368 ,  G02F1/13624

摘要： An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd1. In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd2, the gate-to-drain capacitances of the other active devices are Cgd1, and Cgd1≠Cgd2.

摘要翻译： 有源器件阵列衬底包括衬底，设置在衬底上的扫描线，与扫描线相交的数据线，扫描信号传输线和像素单元。 扫描信号传输线与扫描线相交。 每条扫描信号传输线通过一个节点连接一条扫描线。 像素单元电连接对应的数据线和相应的扫描线，并且包括有源器件和像素电极。 有源器件具有栅极，源极和漏极。 像素电极电连接漏极。 在与节点不相邻的像素单元中，每个有源器件的栅极 - 漏极电容为Cgd1。 在与节点相邻的像素单元中，一些有源器件的栅极至漏极电容为Cgd2，其他有源器件的栅极至漏极电容为Cgd1，Cgd1≠Cgd2。

公开(公告)号：US09881840B2

公开(公告)日：2018-01-30

申请号：US13157179

申请日：2011-06-09

申请人： Yu-Lien Huang ,  Ziwei Fang ,  Tsan-Chun Wang ,  Chii-Ming Wu ,  Chun Hsiung Tsai

发明人： Yu-Lien Huang ,  Ziwei Fang ,  Tsan-Chun Wang ,  Chii-Ming Wu ,  Chun Hsiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/3115 ,  H01L21/033 ,  H01L21/3213

CPC分类号： H01L21/823814 ,  H01L21/0337 ,  H01L21/31155 ,  H01L21/32139 ,  H01L21/823807

摘要： A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

公开(公告)号：US08877599B2

公开(公告)日：2014-11-04

申请号：US13471986

申请日：2012-05-15

申请人： Ziwei Fang ,  Tsan-Chun Wang ,  De-Wei Yu

发明人： Ziwei Fang ,  Tsan-Chun Wang ,  De-Wei Yu

IPC分类号： H01L21/33

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7847

摘要： A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

摘要翻译： 公开了一种具有位错的半导体器件和制造半导体器件的方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供其中具有隔离特性的衬底和覆盖衬底的两个栅极叠层，其中一个栅极堆叠位于隔离特征顶部。 该方法还包括在衬底上执行预非晶体注入工艺。 该方法还包括在衬底上形成应力膜。 该方法还包括对衬底和应力膜进行退火处理。

公开(公告)号：US08723266B2

公开(公告)日：2014-05-13

申请号：US13324257

申请日：2011-12-13

申请人： Chun Hsiung Tsai ,  Tsan-Chun Wang

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

摘要： The embodiments of processes and structures described provide mechanisms for improving the mobility of carriers. A dislocation is formed in a source or drain region between gate structures or between a gate structure and an isolation structure by first amortizing the source or drain region and then recrystallizing the region by using an annealing process with a low pre-heat temperature. A doped epitaxial material may be formed over the recrystallized region. The dislocation and the strain created by the doped epitaxial material in the source or drain region help increase carrier mobility.

摘要翻译： 所描述的方法和结构的实施方案提供了改善载体迁移率的机制。 在栅极结构之间或栅极结构和隔离结构之间的源极或漏极区域中形成位错，首先使源极或漏极区域摊平，然后通过使用具有低预热温度的退火工艺对该区域进行再结晶。 可以在再结晶区域上形成掺杂的外延材料。 在源极或漏极区中由掺杂的外延材料产生的位错和应变有助于增加载流子迁移率。

公开(公告)号：US08471973B2

公开(公告)日：2013-06-25

申请号：US12788876

申请日：2010-05-27

申请人： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

发明人： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC分类号： G02F1/36

CPC分类号： G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

摘要： This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

摘要翻译： 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US20100296016A1

公开(公告)日：2010-11-25

申请号：US12647300

申请日：2009-12-24

申请人： Yu-Cheng CHEN ,  Tsan-Chun Wang ,  Maw-Song Chen

发明人： Yu-Cheng CHEN ,  Tsan-Chun Wang ,  Maw-Song Chen

IPC分类号： G02F1/1343 ,  G02F1/13

CPC分类号： G02F1/136286

摘要： An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate includes a base, scan lines, data lines and gate tracking lines disposed on the base. Each of the gate tracking lines has first portions, auxiliary portions and junction portions, wherein the junction portion and the first portion are formed in different layers. One of the junction portions is electrically connected with corresponding one of the first portions.

摘要翻译： 提供有源阵列基板，液晶显示面板和制造有源阵列基板的方法。 有源阵列基板包括设置在基座上的基极，扫描线，数据线和栅极跟踪线。 每个栅极跟踪线具有第一部分，辅助部分和接合部分，其中接合部分和第一部分形成在不同的层中。 一个接合部分与相应的一个第一部分电连接。

公开(公告)号：US08987099B2

公开(公告)日：2015-03-24

申请号：US13332011

申请日：2011-12-20

申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

IPC分类号： H01L21/336 ,  H01L21/268 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/2686 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

摘要翻译： 本公开提供了在一个实施例中制造集成电路的方法。 该方法包括提供具有有源区的半导体衬底和设置在有源区中的半导体衬底上的第一栅叠层; 在所述半导体衬底上形成原位磷掺杂碳化硅（SiCP）特征并且设置在所述第一栅极叠层的侧面上; 用具有高k介电材料层的第二栅极堆叠代替第一栅极堆叠; 然后进行具有第一热小波和第二热小波的热分布的毫秒退火（MSA）处理。

公开(公告)号：US08916428B2

公开(公告)日：2014-12-23

申请号：US13343891

申请日：2012-01-05

申请人： Tsan-Chun Wang ,  Chun Hsiung Tsai

发明人： Tsan-Chun Wang ,  Chun Hsiung Tsai

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L29/10

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

摘要： A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

摘要翻译： 公开了一种具有位错的半导体器件和制造半导体器件的方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供其中具有隔离特征的衬底和覆盖衬底的两个栅极叠层，其中一个栅极堆叠位于隔离特征顶部。 该方法还包括在衬底上执行预非晶体注入工艺。 所述方法还包括形成邻接所述栅极叠层的侧壁的间隔区，其中所述间隔物中的至少一个延伸超过所述隔离特征的边缘。 该方法还包括在衬底上形成应力膜。 该方法还包括对衬底和应力膜进行退火处理。

公开(公告)号：US08674453B2

公开(公告)日：2014-03-18

申请号：US13324331

申请日：2011-12-13

申请人： Chun Hsiung Tsai ,  Tsan-Chun Wang ,  Su-Hao Liu ,  Tsz-Mei Kwok ,  Chii-Meng Wu

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang ,  Su-Hao Liu ,  Tsz-Mei Kwok ,  Chii-Meng Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/22 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/32 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

摘要翻译： 上述过程和结构的实施例提供了改善载体移动性的机制。 源极和漏极区中的位错以及由晶体管的沟道区旁边的掺杂外延材料产生的应变都有助于沟道区中的应变。 结果，设备性能得到改善。

公开(公告)号：US08629046B2

公开(公告)日：2014-01-14

申请号：US13177309

申请日：2011-07-06

申请人： Chun Hsiung Tsai ,  Tsan-Chun Wang

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang

IPC分类号： H01L21/28 ,  H01L21/22

CPC分类号： H01L27/088 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/7847 ,  H01L29/7848

摘要： A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film.

摘要翻译： 公开了一种具有双层位错的半导体器件和制造半导体器件的方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供具有栅叠层的衬底。 该方法还包括在衬底上执行第一预非晶体注入工艺并在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。