公开(公告)号：US07763978B2

公开(公告)日：2010-07-27

申请号：US11729228

申请日：2007-03-28

Applicant: Wei Wu ,  R. Stanley Williams ,  Warren Robinett ,  Gregory S. Snider ,  Zhaoning Yu ,  Shih-Yuan Wang ,  Duncan Stewart

Inventor： Wei Wu ,  R. Stanley Williams ,  Warren Robinett ,  Gregory S. Snider ,  Zhaoning Yu ,  Shih-Yuan Wang ,  Duncan Stewart

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L27/101 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/81 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.

Abstract translation: 本发明的各种实施例涉及三维横杆阵列。 在本发明的一个方面，三维交叉开关阵列包括多个交叉开关阵列，第一解复用器，第二解复用器和第三解复用器。 每个横杆阵列包括第一纳米线层，覆盖第一纳米线层的第二纳米线层和覆盖第二纳米线层的第三层纳米线。 第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向 纳米线在每个交叉列阵列的第三层纳米线中。

公开(公告)号：US20070176801A1

公开(公告)日：2007-08-02

申请号：US11343325

申请日：2006-01-30

Applicant: Warren Robinett ,  Gregory Snider ,  Duncan Stewart ,  Joseph Straznicky

Inventor： Warren Robinett ,  Gregory Snider ,  Duncan Stewart ,  Joseph Straznicky

IPC: H03M7/00

CPC classification number: G11C8/10 ,  G11C13/0023 ,  H03M13/51

Abstract: Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.

Abstract translation: 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位， 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联， 代码字内部地址。

公开(公告)号：US07982504B1

公开(公告)日：2011-07-19

申请号：US12696361

申请日：2010-01-29

Applicant: Warren Robinett

Inventor： Warren Robinett

IPC: H03K19/00

CPC classification number: H01L27/0688 ,  H01L21/823871 ,  H01L27/101 ,  H01L27/2481

Abstract: An interconnection architecture for multilayer circuits includes an array of vias and a CMOS layer configured to selectively access the array of vias according to an address. The interconnection architecture also includes a crossbar stack which includes layers of intersecting wire segments with programmable crosspoint devices interposed between intersecting wire segments. The vias are connected to the wire segments such that each programmable crosspoint device is uniquely addressed and every address within a contiguous address space accesses a programmable crosspoint device.

Abstract translation: 用于多层电路的互连架构包括通孔阵列和被配置为根据地址选择性地访问通孔阵列的CMOS层。 互连架构还包括横梁堆叠，其包括交替的线段的层，其间插入有交叉线段之间的可编程交叉点设备。 通孔连接到线段，使得每个可编程交叉点设备被唯一地寻址，并且连续地址空间内的每个地址访问可编程交叉点设备。

公开(公告)号：US07872502B2

公开(公告)日：2011-01-18

申请号：US11484961

申请日：2006-07-12

Applicant: Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

Inventor： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: H03K19/094

CPC classification number: H03K19/007 ,  G06F11/1076 ,  H03K19/00315

Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

Abstract translation: 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

公开(公告)号：US20100293518A1

公开(公告)日：2010-11-18

申请号：US12011175

申请日：2008-01-23

Applicant: Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

Inventor： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

IPC: G06F17/50

CPC classification number: G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

Abstract translation: 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，采用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，均匀分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。

公开(公告)号：US20100091662A1

公开(公告)日：2010-04-15

申请号：US12288035

申请日：2008-10-15

Applicant: Ron M. Roth ,  Joseph Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

Inventor： Ron M. Roth ,  Joseph Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: H04J3/14

CPC classification number: H04J3/047 ,  H03K17/002 ,  H03K19/0021 ,  H03K19/003

Abstract: Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.

Abstract translation: 本发明的实施例包括采用阈值逻辑“TL”元素的采用或可以通过解复用器交叉开关建模的缺陷容许解复用器交叉开关。 阈值逻辑元件提供了对于容错解复用器交叉开关的内部信号线上的信号变化的容限，并因此提供产生内部信号变化的缺陷的容限。

公开(公告)号：US20080237886A1

公开(公告)日：2008-10-02

申请号：US11729228

申请日：2007-03-28

Applicant: Wei Wu ,  R. Stanley Williams ,  Warren Robinett ,  Gregory S. Snider ,  Zhaoning Yu ,  Shih-Yuan Wang ,  Duncan Stewart

Inventor： Wei Wu ,  R. Stanley Williams ,  Warren Robinett ,  Gregory S. Snider ,  Zhaoning Yu ,  Shih-Yuan Wang ,  Duncan Stewart

IPC: H01L23/48

CPC classification number: H01L27/101 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/81 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.

Abstract translation: 本发明的各种实施例涉及三维横杆阵列。 在本发明的一个方面，三维交叉开关阵列包括多个交叉开关阵列，第一解复用器，第二解复用器和第三解复用器。 每个横杆阵列包括第一纳米线层，覆盖第一纳米线层的第二纳米线层和覆盖第二纳米线层的第三层纳米线。 第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向 纳米线在每个交叉列阵列的第三层纳米线中。

公开(公告)号：US20080094629A1

公开(公告)日：2008-04-24

申请号：US11584461

申请日：2006-10-20

Applicant: Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

Inventor： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

IPC: G01B11/00

CPC classification number: G03F9/7049 ,  G03F9/7003

Abstract: Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

Abstract translation: 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

公开(公告)号：US20080013393A1

公开(公告)日：2008-01-17

申请号：US11484961

申请日：2006-07-12

Applicant: Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

Inventor： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: G11C17/18

CPC classification number: H03K19/007 ,  G06F11/1076 ,  H03K19/00315

Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

Abstract translation: 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

公开(公告)号：US08773167B2

公开(公告)日：2014-07-08

申请号：US13561978

申请日：2012-07-30

Applicant: Warren Robinett ,  R. Stanley Williams

Inventor： Warren Robinett ,  R. Stanley Williams

IPC: H03K19/00 ,  G11C11/00

CPC classification number: H03K19/173 ,  G11C13/0007 ,  H03K19/17712 ,  H03K19/17728

Abstract: Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

Abstract translation: 使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。 至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。 至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态 。