公开(公告)号：US20140329845A1

公开(公告)日：2014-11-06

申请号：US14196186

申请日：2014-03-04

Applicant: Sean G. Trapp ,  Michael R. Leadbetter ,  Daniel D. Long ,  Pierre-Jean Colson ,  Miroslav Rapta ,  Ying Yu

Inventor： Sean G. Trapp ,  Michael R. Leadbetter ,  Daniel D. Long ,  Pierre-Jean Colson ,  Miroslav Rapta ,  Ying Yu

IPC: C07C237/48 ,  A61K45/06 ,  A61K31/197

CPC classification number: C07C237/48 ,  A61K9/0075 ,  A61K9/2054 ,  A61K9/4858 ,  A61K31/197 ,  A61K31/485 ,  A61K45/06 ,  A61K47/02 ,  A61K47/12 ,  C07B2200/07 ,  C07C215/64 ,  C07C229/28 ,  C07C229/34 ,  C07C2601/14 ,  C07C2602/10 ,  Y10T436/173845

Abstract: The invention provides 3-carboxypropyl-aminotetralin compounds of formula (I): wherein R1, R2, R3, R4, R5, and R6 are defined in the specification, or a pharmaceutically-acceptable salt thereof, that are antagonists at the mu opioid receptor. The invention also provides pharmaceutical compositions comprising such compounds, methods of using such compounds to treat conditions associated with mu opioid receptor activity, and processes and intermediates useful for preparing such compounds.

Abstract translation: 本发明提供式（I）的3-羧基丙基 - 氨基四氢化茚化合物：其中R1，R2，R3，R4，R5和R6在本说明书中定义，或其药学上可接受的盐，其为μ阿片受体 。 本发明还提供包含这些化合物的药物组合物，使用这些化合物治疗与阿片样物质受体活性相关的病症的方法，以及可用于制备这些化合物的方法和中间体。

公开(公告)号：US20130187677A1

公开(公告)日：2013-07-25

申请号：US13355024

申请日：2012-01-20

Applicant: Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

Inventor： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: G01R31/26

CPC classification number: H03K3/012 ,  G01R31/26 ,  G01R31/2607 ,  G01R31/3004 ,  G01R31/3191 ,  G01R31/31924 ,  G01R31/3193 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/0002 ,  H03K3/017 ,  H03K17/94 ,  H01L2924/00

Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

公开(公告)号：US08482987B2

公开(公告)日：2013-07-09

申请号：US12875003

申请日：2010-09-02

Applicant: Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

Inventor： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/345 ,  G11C16/3454

Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

公开(公告)号：US20130117613A1

公开(公告)日：2013-05-09

申请号：US13602031

申请日：2012-08-31

Applicant: Ying Yu Tai ,  Yueh Yale Ma

Inventor： Ying Yu Tai ,  Yueh Yale Ma

IPC: G06F12/00 ,  G06F11/07

CPC classification number: G06F11/1048 ,  G11C11/5642 ,  G11C16/26

Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.

Abstract translation: 实施方式包括适用于存储器系统的系统，方法和/或设备，其可以增强用于提高数据可被存储和读取的可靠性的错误控制代码的性能。 一些实施方式包括能够生成和利用软信息来解码从存储介质读取的编码数据的系统，方法和/或设备。 更具体地，一些实施方案利用包括用于比特元组的软信息值的表征向量的集合，所述比特元组可以从存储介质读取用于存储介质表征参数值的各种组合。 一些实施方式能够确定和利用与一个或多个存储介质表征参数值相关联的读取比较信号值。 并且一些实施方式能够确定和利用与一个或多个存储介质表征参数值和识别的错误条件相关联的移位读取比较信号值。

公开(公告)号：US08410818B1

公开(公告)日：2013-04-02

申请号：US13372978

申请日：2012-02-14

Applicant: Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: H03K19/094

CPC classification number: H03K3/012 ,  H03K19/0013 ,  H03K19/018521

Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

公开(公告)号：US20130003204A1

公开(公告)日：2013-01-03

申请号：US13275317

申请日：2011-10-18

Applicant: Tsung-Dar Cheng ,  Jen-You Chu ,  Ding-Zheng Lin ,  Yi-Ping Chen ,  Jia-Han Li ,  Hsin-Hung Cheng ,  Ying-Yu Chang

Inventor： Tsung-Dar Cheng ,  Jen-You Chu ,  Ding-Zheng Lin ,  Yi-Ping Chen ,  Jia-Han Li ,  Hsin-Hung Cheng ,  Ying-Yu Chang

IPC: G02B5/09

CPC classification number: H01L31/0547 ,  G02B19/0028 ,  G02B19/0042 ,  G02B19/0061 ,  H01L31/02168 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/054 ,  Y02E10/52

Abstract: A multi-reflection structure including a substrate and pyramid is provided. The substrate includes an inversed pyramid shaped recess having at least three first reflection sidewalls. The pyramid is disposed on the substrate and located in the inversed pyramid shaped recess. The pyramid has at least three second reflection sidewalls, wherein the normal of each of the second reflection sidewalls and the normal of each of the first reflection sidewalls are not located in the same plane. Furthermore, a photo-electric device is also provided in the present application.

Abstract translation: 提供了包括基板和金字塔的多反射结构。 衬底包括具有至少三个第一反射侧壁的反转金字塔形凹部。 金字塔设置在基板上并且位于反转的金字塔形凹部中。 金字塔具有至少三个第二反射侧壁，其中每个第二反射侧壁的法线和每个第一反射侧壁的法线不位于同一平面内。 此外，在本申请中还提供了光电装置。

公开(公告)号：US08203896B2

公开(公告)日：2012-06-19

申请号：US12911173

申请日：2010-10-25

Applicant: Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

Inventor： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

IPC: G11C7/00 ,  G11C11/50 ,  G11C7/04

CPC classification number: G11C29/022 ,  G11C29/02

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract translation: 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US08190936B2

公开(公告)日：2012-05-29

申请号：US12194045

申请日：2008-08-19

Applicant: Tuan Che Chen ,  Ying Yu Chen ,  Jyh-Cheng Chen

Inventor： Tuan Che Chen ,  Ying Yu Chen ,  Jyh-Cheng Chen

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G08C17/00

CPC classification number: G06F1/3203 ,  G06F1/329 ,  H04W28/18 ,  H04W52/0216 ,  Y02D10/24 ,  Y02D70/146 ,  Y02D70/21

Abstract: The method for maximizing an unavailability interval includes the steps of initializing the starting frame number of each power saving class fi to 1 and adjusting fi to fi′ when the least common multiple of m1, m2, . . . , mi−1 and mi is not relatively prime. The index i is an integer from 1 to t, mi is the sleep cycle of the ith power saving class, and fi′ is an integer that maximizes common sleep windows of the i power saving classes. The common sleep windows of the t power saving classes are then set as the maximum unavailability interval of the wireless telecommunication device.

Abstract translation: 最大化不可用性间隔的方法包括以下步骤：将每个省电等级fi的起始帧号初始化为1，并且在m1，m2的最小公倍数时调整fi至fi'。 。 。 ，mi-1和mi并不相关。 索引i是从1到t的整数，mi是第i个省电类的睡眠周期，fi'是使i节能类的常见睡眠窗口最大化的整数。 然后将t节电等级的公共睡眠窗口设置为无线电信设备的最大不可用间隔。

公开(公告)号：US20110214106A1

公开(公告)日：2011-09-01

申请号：US13024493

申请日：2011-02-10

Applicant: Yao Qi ,  Wei Ying Yu ,  Yong Zheng

Inventor： Yao Qi ,  Wei Ying Yu ,  Yong Zheng

IPC: G06F9/44

CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F2201/865

Abstract: A method, computer program product and apparatus for indicating program modifications affecting program performance in an Integrated Development Environment (IDE). The modifications that a developer makes to a program is detected and the code location where these modifications occur is determined. The previous profiling data of the program is acquired. The effect of the modifications on the program performance according to the previous profiling data and the code location where the modifications occur is evaluated. The evaluation results may then be provided to the developer. As a result of the above process, the developer can be aware of the performance problem while he/she is editing the source code so as to make corrections without waiting after the profiling phase, thus greatly shortening the development period.

Abstract translation: 一种在集成开发环境（IDE）中指示影响程序性能的程序修改的方法，计算机程序产品和装置。 检测到开发者对程序的修改，并确定发生这些修改的代码位置。 获取程序的以前的分析数据。 评估根据先前的分析数据和修改发生的代码位置对修改对程序性能的影响。 然后可以向开发者提供评估结果。 作为上述过程的结果，开发人员在编辑源代码时可以了解性能问题，以便在分析阶段之后进行更正，而无需等待，从而大大缩短开发周期。

公开(公告)号：US20110115551A1

公开(公告)日：2011-05-19

申请号：US12786122

申请日：2010-05-24

Applicant: Chun-Hsiung Hung ,  Chuan-Ying Yu

Inventor： Chun-Hsiung Hung ,  Chuan-Ying Yu

IPC: G05F3/02

CPC classification number: H02M3/073

Abstract: A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.

Abstract translation: 在集成电路中产生泵浦电压的方法包括从集成电路的外部接收外部时钟信号。 接收到的外部时钟信号的频率根据一个或多个调制比而改变，导致一个或多个相应调制的外部时钟信号。 然后选择外部时钟信号或调制的外部时钟信号之一用作泵浦时钟信号。 泵时钟信号用于驱动泵电路的泵电容以产生泵浦电压。