公开(公告)号：US06870216B2

公开(公告)日：2005-03-22

申请号：US10606702

申请日：2003-06-26

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/72

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract translation: 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。

公开(公告)号：US06808987B2

公开(公告)日：2004-10-26

申请号：US10460796

申请日：2003-06-12

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A method for forming a vertical nitride read-only memory cell. A substrate having at least one trench is provided. A first conductive layer is formed in the lower trench and insulated from the substrate to serve as a source line. A first doping region is formed in the substrate adjacent to the top of the first conductive layer. A first insulating layer is formed on the first conductive layer. A second doping region is formed in the substrate adjacent to the top of the trench. A second insulating layer is formed over the sidewall of the trench and on the first insulating layer to serve as a gate dielectric layer. A second conductive layer is formed in the upper trench to serve as a control gate. A vertical nitride read-only memory cell is also disclosed.

Abstract translation: 一种用于形成垂直氮化物只读存储单元的方法。 提供具有至少一个沟槽的衬底。 第一导电层形成在下沟槽中并与衬底绝缘以用作源极线。 第一掺杂区形成在与第一导电层的顶部相邻的衬底中。 在第一导电层上形成第一绝缘层。 第二掺杂区形成在邻近沟槽顶部的衬底中。 第二绝缘层形成在沟槽的侧壁和第一绝缘层上，用作栅极介电层。 第二导电层形成在上沟槽中用作控制栅极。 还公开了一种垂直氮化物只读存储单元。

公开(公告)号：US20140252532A1

公开(公告)日：2014-09-11

申请号：US13792231

申请日：2013-03-11

Applicant: Sheng-Wei Yang ,  Ying-Cheng Chuang ,  Shyam Surthi

Inventor： Sheng-Wei Yang ,  Ying-Cheng Chuang ,  Shyam Surthi

IPC: H01L29/06 ,  H01L21/765

CPC classification number: H01L21/765 ,  H01L21/265 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/10876 ,  H01L29/0607 ,  H01L29/407 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827

Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 提供具有多个支柱的基板，其中围绕每个支柱形成多个沟槽。 在衬底中并在每个柱下方形成掺杂区域。 去除每个沟槽下方的掺杂区域以形成开口，使得相邻支柱之下的掺杂区域彼此分离。 在每个开口中形成屏蔽层。

公开(公告)号：US20120119276A1

公开(公告)日：2012-05-17

申请号：US12945423

申请日：2010-11-12

Applicant: YING CHENG CHUANG ,  PING CHENG HSU ,  SHENG WEI YANG ,  MING CHENG CHANG ,  HUNG MING TSAI

Inventor： YING CHENG CHUANG ,  PING CHENG HSU ,  SHENG WEI YANG ,  MING CHENG CHANG ,  HUNG MING TSAI

IPC: H01L27/108 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/76229 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

Abstract translation: 存储器件包括台面结构和字线。 具有两个相对侧表面的台面结构包括至少一对源极/漏极区域和与其中形成的一对源极/漏极区域对应的至少一个沟道基极区域。 字线包括两个线性部分和至少一个互连部分。 每个线性部分在台面结构的相邻侧表面上延伸，邻近通道基底区域。 至少一个互连部分穿过台面结构，连接两个线性部分。

公开(公告)号：US07700991B2

公开(公告)日：2010-04-20

申请号：US11946868

申请日：2007-11-29

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

Abstract translation: 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20090014886A1

公开(公告)日：2009-01-15

申请号：US11951274

申请日：2007-12-05

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H02H9/00

CPC classification number: H01L27/0251 ,  H01L27/10894

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract translation: 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

公开(公告)号：US07205603B2

公开(公告)日：2007-04-17

申请号：US10764037

申请日：2004-01-23

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

公开(公告)号：US06872623B2

公开(公告)日：2005-03-29

申请号：US10395991

申请日：2003-03-24

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US06770532B2

公开(公告)日：2004-08-03

申请号：US10435447

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6656

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract translation: 一种用于制造具有T形门的存储器单元的方法。 在CMOS工艺中提供形成电介质层，第一开口和第二开口的半导体衬底。 硅酸盐玻璃间隔物形成在第一开口的侧壁上，并被热氧化以在硅酸盐玻璃间隔物下面形成光掺杂区域。 去除硅酸盐玻璃间隔物。 绝缘垫片形成在第一开口的侧壁上。 第一间隔件形成在第二开口的侧壁上。 分别在绝缘间隔物和第一间隔物的侧壁上形成N型导电间隔物。 栅电介质层分别形成在第一开口和第二开口中。 P型导电层填充有第一开口和第二开口，并且第二间隔件形成在第二开口的导电间隔件的侧壁上。

公开(公告)号：US08415728B2

公开(公告)日：2013-04-09

申请号：US12945423

申请日：2010-11-12

Applicant: Ying Cheng Chuang ,  Ping Cheng Hsu ,  Sheng Wei Yang ,  Ming Cheng Chang ,  Hung Ming Tsai

Inventor： Ying Cheng Chuang ,  Ping Cheng Hsu ,  Sheng Wei Yang ,  Ming Cheng Chang ,  Hung Ming Tsai

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/76229 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

Abstract translation: 存储器件包括台面结构和字线。 具有两个相对侧表面的台面结构包括至少一对源极/漏极区域和与其中形成的一对源极/漏极区域对应的至少一个沟道基极区域。 字线包括两个线性部分和至少一个互连部分。 每个线性部分在台面结构的相邻侧表面上延伸，邻近通道基底区域。 至少一个互连部分穿过台面结构，连接两个线性部分。