Abstract:
A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a surface of the insulating layer outside the trench. Related structures are also disclosed.
Abstract:
A platen structure of a polishing apparatus for semiconductor wafer and a method for exchanging a polishing pad affixed to the same are provided in which the polishing pad supported by the platen is exchanged with convenience within a short time. The platen structure of the polishing apparatus in which the polishing pad attached to the platen of the polishing apparatus comprises a pad plate to which the polishing pad for polishing a wafer is attached, and a platen body combined with the pad plate and having at least one vacuum hole formed thereto to provide a vacuum passage.
Abstract:
An apparatus for polishing a wafer is provided. The apparatus comprises a polishing pad for polishing the wafer. The polishing pad is divided into multiple portions that are rotated in a substantially same direction. At least one of the portions of the polishing pad is adapted to rotate at a speed different than the other portions. A driving unit is also provided for moving the polishing pad. A polishing head is employed for maintaining the side of the wafer to be polished engaged with the polishing pad, for contacting the polished surface of the wafer with the polishing pad, and for rotating the wafer.
Abstract:
The chemical mechanical polishing (CMP) apparatus includes an insert pad that forms a local step on an upper surface of a polishing pad assembly. The insert pad is interposed between a rotatable platen and the polishing pad assembly.
Abstract:
A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).
Abstract:
Methods for manufacturing a semiconductor device, in which a chamfered metal silicide layer is formed by a 2-stage continuous wet etching process using different etchants, thereby resulting in a sufficient insulation margin between a lower conductive layer including the metal silicide layer and the contact plug self-aligned with the lower conductive layer are disclosed. In the manufacture of a semiconductor device, a mask pattern is formed on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove, and defects due to the silicon remaining on the surface of the metal silicide layer with the shallow groove are removed using a second etchant, to form a metal silicide layer with a smooth surface. Microelectronic structures produced by methods of the present invention are also disclosed.
Abstract:
Solutions useful for etching semiconductor devices comprise ammonium fluoride, hydrofluoric acid, hydrogen peroxide, and water. Processes for forming the solutions comprise mixing first solutions which comprise ammonium fluoride, hydrofluoric acid, and water with second solutions which comprise hydrogen peroxide and water to form the solutions of the invention. Methods for etching semiconductor devices comprise contacting the devices which comprise a substrate and oxide layer thereon with the solutions of the invention to etch the devices. The oxide layer, for example a damaged silicon oxide layer on a silicon substrate, is selectively etched to the substrate.
Abstract:
A sealing member includes a body having a ring shape, a lower contacting portion protruding from a lower end of the body and having at least one recess, the recess provided in a lower surface of the lower contacting portion and extending in a radial direction of the body, and an outer contacting portion protruding outwards from the body along an outer side portion of the body.
Abstract:
In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.
Abstract:
Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. The electrode structure may include a pad, a first insulation layer pattern, a second insulation layer pattern and/or an electrode. The first insulation layer pattern may be formed on the pad. The first insulation layer pattern may have a first opening that partially exposes the pad. The second insulation layer pattern may be formed on the first insulation layer pattern. The second insulation layer pattern may have a second opening connected to the first opening. The electrode may be formed on the pad and filling the first and the second openings.