公开(公告)号：US20080180185A1

公开(公告)日：2008-07-31

申请号：US11701303

申请日：2007-01-31

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L5/00 ,  H03B5/12

CPC classification number: H03L5/00 ,  H03L7/099 ,  H03L2207/06

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract translation: 公开了用于控制由VCO产生的信号的幅度的电路和方法。

公开(公告)号：US5548137A

公开(公告)日：1996-08-20

申请号：US207327

申请日：1994-03-07

Applicant: Yongping Fan ,  Jung Han ,  Arto V. Nurimikko ,  Robert L. Gunshor ,  Li He

Inventor： Yongping Fan ,  Jung Han ,  Arto V. Nurimikko ,  Robert L. Gunshor ,  Li He

IPC: H01L21/36 ,  H01L21/44 ,  H01L27/15 ,  H01L33/06 ,  H01L33/08 ,  H01L33/14 ,  H01L33/26 ,  H01L33/28 ,  H01L33/40 ,  H01S5/042 ,  H01S5/223 ,  H01S5/347 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01S5/347 ,  B82Y20/00 ,  H01L21/02395 ,  H01L21/024 ,  H01L21/02417 ,  H01L21/02469 ,  H01L21/02485 ,  H01L21/0251 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/44 ,  H01L33/06 ,  H01L33/08 ,  H01L33/14 ,  H01S5/0421 ,  H01L27/156 ,  H01L33/26 ,  H01L33/28 ,  H01L33/40 ,  H01S5/2231

Abstract: Group II-VI compound semiconductor light emitting devices which include at least one II-VI quantum well region of a well layer disposed between first and second barrier layers is disclosed. The quantum well region is sandwiched between first and second cladding layers of a II-VI semiconductor material. The first cladding layer is formed on and lattice matched to the first barrier layer and to a substrate of a III-V compound semiconductor material. The second cladding layer is lattice matched to the second barrier layer. The quantum well layer comprises a II-VI compound semiconductor material having the formula A.sub.x B.sub.(1-x) C wherein A and B are two different elements from Group II and C is at least one element from Group VI. When the second cladding layer has a p-type conductivity, a graded bandgap ohmic contact according to the present invention can be utilized. The graded bandgap contact can be a single continuously graded II-VI p-type region or a plurality of cells with each of the cells having first and second thin layers of first and second p-type II-VI semiconductor materials respectively. Another embodiment of the present invention discloses a monolithic multicolor light emitting element capable of emitting four colors and a method for fabricating same. The monolithic multicolor element includes four II-VI semiconductor light emitting devices formed on a single III-V substrate.

Abstract translation: 公开了包括设置在第一和第二阻挡层之间的阱层的至少一个II-VI量子阱区的II-VI族化合物半导体发光器件。 量子阱区夹在II-VI半导体材料的第一和第二覆层之间。 第一包层与第一阻挡层和III-V族化合物半导体材料的衬底形成并晶格匹配。 第二包层与第二阻挡层晶格匹配。 量子阱层包括具有式AxB（1-x）C的II-VI化合物半导体材料，其中A和B是来自组II的两个不同元素，C是来自第VI族的至少一种元素。 当第二包覆层具有p型导电性时，可以使用根据本发明的渐变带隙欧姆接触。 分级带隙接触可以是单个连续分级的II-VI p型区域或多个单元，其中每个单元分别具有第一和第二p型II-VI半导体材料的第一和第二薄层。 本发明的另一实施例公开了能够发射四种颜色的单片多色发光元件及其制造方法。 单片多色元件包括形成在单个III-V衬底上的四个II-VI半导体发光器件。

公开(公告)号：US20110148480A1

公开(公告)日：2011-06-23

申请号：US12640189

申请日：2009-12-17

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03K23/00

CPC classification number: H03K23/544 ,  G06F1/04

Abstract: A divider is disclosed that presents an enhanced duty cycle for use with precision oscillators in clock sources. In one example, the invention includes a first divider chain to receive an input clock and produce a first divided output, a second divider chain to receive the input clock and produce a second divided output, and a combiner to combine the first and second divided output to produce a third divided output with a duty cycle greater than the first and second divided output.

Abstract translation: 公开了一种分频器，其提供与时钟源中的精密振荡器一起使用的增强占空比。 在一个示例中，本发明包括第一分频器链，用于接收输入时钟并产生第一分频输出，第二分频器链接收输入时钟并产生第二分频输出，以及组合器，以组合第一和第二分频输出 以产生占空比大于第一和第二分频输出的第三分频输出。

公开(公告)号：US07593496B2

公开(公告)日：2009-09-22

申请号：US11319879

申请日：2005-12-27

Applicant: Yongping Fan ,  Ian A. Young

Inventor： Yongping Fan ,  Ian A. Young

IPC: H04L7/00

CPC classification number: H03H11/16 ,  H04L7/0338

Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

Abstract translation: 相位插值器包括产生具有第一相位延迟的第一信号和具有第二相位延迟的第二信号和相位混频器的第一电路。 耦合相位混合器以接收来自第一电路的第一和第二信号。 相位混合器包括多个电流驱动器，每个电流驱动器包括耦合以选择性地延迟第一或第二信号中的一个的电流驱动器输入和耦合以输出相位延迟信号的电流驱动器输出。 电流驱动器的当前驱动器输出耦合在一起以组合来自电流驱动器的相位延迟信号，以产生具有从第一和第二信号内插的相位的输出相位延迟信号。

公开(公告)号：US07501904B2

公开(公告)日：2009-03-10

申请号：US11592591

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03K3/03

CPC classification number: H03L7/0995 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/00136 ,  H03L7/0891 ,  H03L7/18

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract translation: 具有压控振荡器的锁相环，其中压控振荡器包括反馈回路和以环形连接的延迟单元。 每个延迟单元具有偏置的pMOSFET以提供上拉电流和偏置的nMOSFET以提供下拉电流。 对于每个延迟单元，偏置的nMOSFET的栅极被由锁相环提供的控制电压偏置，并且偏置的pMOSFET的栅极被偏置在由反馈环路提供的偏置电压。 调整pMOSFET的偏置，使得每个延迟单元的上拉和下拉电流匹配，从而提供50％的占空比以及在处理，电源电压变化和温度变化方面的良好的抖动性能。 因为只有反馈回路具有非零静态电流，所以预期功耗低。 描述和要求保护其他实施例。

公开(公告)号：US07471157B2

公开(公告)日：2008-12-30

申请号：US11471756

申请日：2006-06-20

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03L7/00

CPC classification number: H03L7/0812 ,  H03L7/0895

Abstract: A charge pump that generates a bias input to affect an output voltage of the charge pump is described herein. The charge pump may include a charge pump stage, a replica charge pump stage, and a self-biased differential amplifier. In some instances, the charge pump may be incorporated into a delay locked loop or a phase locked loop.

Abstract translation: 这里描述了产生偏置输入以影响电荷泵的输出电压的电荷泵。 电荷泵可以包括电荷泵级，复制电荷泵级和自偏置差分放大器。 在一些情况下，电荷泵可以并入到延迟锁定环或锁相环中。

公开(公告)号：US07327174B2

公开(公告)日：2008-02-05

申请号：US11374808

申请日：2006-03-14

Applicant: Yongping Fan ,  Ian A. Young

Inventor： Yongping Fan ,  Ian A. Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0891 ,  H03L7/10

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.

Abstract translation: 用于延迟锁定环和锁相环的快速锁定机制。 第一电路被耦合以接收输入时钟信号并响应于输入时钟信号产生输出时钟信号。 第一电路包括电荷泵和延迟单元。 电荷泵在第一电路的操作期间产生操作偏置电压以控制延迟单元的延迟。 快速锁定电路耦合到电荷泵的输出端，以在启用电荷泵之前以启动偏置电压对电荷泵的输出进行预充电。

公开(公告)号：US20080007347A1

公开(公告)日：2008-01-10

申请号：US11471756

申请日：2006-06-20

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03L7/00

CPC classification number: H03L7/0812 ,  H03L7/0895

Abstract: A charge pump that generates a bias input to affect an output voltage of the charge pump is described herein. The charge pump may include a charge pump stage, a replica charge pump stage, and a self-biased differential amplifier. In some instances, the charge pump may be incorporated into a delay locked loop or a phase locked loop.

Abstract translation: 这里描述了产生偏置输入以影响电荷泵的输出电压的电荷泵。 电荷泵可以包括电荷泵级，复制电荷泵级和自偏置差分放大器。 在一些情况下，电荷泵可以并入到延迟锁定环或锁相环中。

公开(公告)号：US20070147564A1

公开(公告)日：2007-06-28

申请号：US11319879

申请日：2005-12-27

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H04L7/00 ,  H04L7/04 ,  H03H11/16

CPC classification number: H03H11/16 ,  H04L7/0338

Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

Abstract translation: 相位插值器包括产生具有第一相位延迟的第一信号和具有第二相位延迟的第二信号和相位混频器的第一电路。 耦合相位混合器以接收来自第一电路的第一和第二信号。 相位混合器包括多个电流驱动器，每个电流驱动器包括耦合以选择性地延迟第一或第二信号中的一个的电流驱动器输入和耦合以输出相位延迟信号的电流驱动器输出。 电流驱动器的当前驱动器输出耦合在一起以组合来自电流驱动器的相位延迟信号，以产生具有从第一和第二信号内插的相位的输出相位延迟信号。

公开(公告)号：US07102200B2

公开(公告)日：2006-09-05

申请号：US09944222

申请日：2001-09-04

Applicant: Yongping Fan ,  Jeffrey E Smith

Inventor： Yongping Fan ,  Jeffrey E Smith

IPC: H01L27/06 ,  H03K17/16

CPC classification number: H01L27/0629

Abstract: An on-die termination resistor includes three transistors and a resistor. The resistor keeps at least one of the transistors from entering the saturation region and therefore improves the I-V characteristics of the termination resistor.