公开(公告)号：US20120039141A1

公开(公告)日：2012-02-16

申请号：US13209010

申请日：2011-08-12

Applicant: Yu Hwan RO ,  Beak Hyung CHO ,  Ki Whan SONG ,  Young Don CHOI

Inventor： Yu Hwan RO ,  Beak Hyung CHO ,  Ki Whan SONG ,  Young Don CHOI

IPC: G11C7/12

CPC classification number: G11C11/4094 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

Abstract translation: 提供了一种存储器件，其包括多个全局位线，放电线，配置成响应于放电使能信号将多个全局位线连接到放电线的开关电路，配置为施加的第一放电电路 第一电压，其高于对所述放电线的接地电压;预充电电路，被配置为对所述多个全局位线中的所选择的全局位线施加预充电电压;以及第二放电电路，被配置为将所选择的全局位 线路到高于接地电压的第二电压。

公开(公告)号：US07817479B2

公开(公告)日：2010-10-19

申请号：US12136822

申请日：2008-06-11

Applicant: Yu-Hwan Ro ,  Byung-Gil Choi ,  In-Cheol Shin

Inventor： Yu-Hwan Ro ,  Byung-Gil Choi ,  In-Cheol Shin

IPC: G11C16/04

CPC classification number: G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

Abstract: A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.

Abstract translation: 使用提供在存储器件外部的电压和在器件内产生的电压而不是仅使用在器件内产生的电压作为驱动电压的非易失性存储器件避免了当出现瞬时显着电压下降时存储器件的故障。 非易失性存储器件包括多个非易失性存储器单元，耦合到多个非易失性存储器单元的至少一部分的位线，耦合到位线的列选择晶体管和驱动电路。 驱动电路耦合到列选择晶体管的栅极，并且被配置为使用其中第二电压高于第一电压的第一电压和第二电压向栅极提供电荷。

公开(公告)号：US07499316B2

公开(公告)日：2009-03-03

申请号：US11723354

申请日：2007-03-19

Applicant: Byung-Gil Choi ,  Du-Eung Kim ,  Yu-Hwan Ro ,  Joon-Yong Choi ,  Beak-Hyung Cho ,  Woo-Yeong Cho

Inventor： Byung-Gil Choi ,  Du-Eung Kim ,  Yu-Hwan Ro ,  Joon-Yong Choi ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/72

Abstract: A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.

Abstract translation: 公开了一种相变存储器件。 其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。 写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

公开(公告)号：US20090003048A1

公开(公告)日：2009-01-01

申请号：US12136822

申请日：2008-06-11

Applicant: Yu-Hwan RO ,  Byung-Gil CHOI ,  In-Cheol SHIN

Inventor： Yu-Hwan RO ,  Byung-Gil CHOI ,  In-Cheol SHIN

IPC: G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

Abstract: A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.

Abstract translation: 使用提供在存储器件外部的电压和在器件内产生的电压而不是仅使用在器件内产生的电压作为驱动电压的非易失性存储器件避免了当出现瞬时显着电压下降时存储器件的故障。 非易失性存储器件包括多个非易失性存储器单元，耦合到多个非易失性存储器单元的至少一部分的位线，耦合到位线的列选择晶体管和驱动电路。 驱动电路耦合到列选择晶体管的栅极，并且被配置为使用其中第二电压高于第一电压的第一电压和第二电压向栅极提供电荷。

公开(公告)号：US08250289B2

公开(公告)日：2012-08-21

申请号：US12402006

申请日：2009-03-11

Applicant: Yu-hwan Ro ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

Inventor： Yu-hwan Ro ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0223 ,  Y02D10/13

Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.

Abstract translation: 半导体存储器件包括存储单元阵列，存储单元阵列包括：多个存储块和至少一个设置单元。 所述至少一个设置单元将存储引导数据的多个存储块内的引导数据存储区域的位置和大小存储起来。 至少一个设置单元可以包括用于将每个存储器块的使用设置为引导块的寄存器。 半导体器件可以是相变存储器。

公开(公告)号：US08243542B2

公开(公告)日：2012-08-14

申请号：US12691769

申请日：2010-01-22

Applicant: Junsoo Bae ,  Dueung Kim ,  Kwangjin Lee ,  Hyungrok Oh ,  Beakhyung Cho ,  Byunggil Choi ,  Woo-Yeong Cho ,  Yu-Hwan Ro

Inventor： Junsoo Bae ,  Dueung Kim ,  Kwangjin Lee ,  Hyungrok Oh ,  Beakhyung Cho ,  Byunggil Choi ,  Woo-Yeong Cho ,  Yu-Hwan Ro

IPC: G11C7/00

CPC classification number: G11C8/10 ,  G11C5/145 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/72

Abstract: A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline using the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage.

Abstract translation: 电阻可变存储器件包括存储单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元可以例如包括电阻可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路使用高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较。

公开(公告)号：US20100284221A1

公开(公告)日：2010-11-11

申请号：US12659690

申请日：2010-03-17

Applicant: Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

Inventor： Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

IPC: G11C16/04

CPC classification number: G11C16/08

Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Abstract translation: 非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。 本地线分别对应于全局选择线。 第一选择电路被配置为连接到全局选择线以选择全局选择线。 第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。 第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

公开(公告)号：US07808815B2

公开(公告)日：2010-10-05

申请号：US11865491

申请日：2007-10-01

Applicant: Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

Inventor： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC: G11C11/00

CPC classification number: G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract translation: 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

公开(公告)号：US07573766B2

公开(公告)日：2009-08-11

申请号：US11898125

申请日：2007-09-10

Applicant: Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

Inventor： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC: G11C29/00

CPC classification number: G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

Abstract translation: 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US07486536B2

公开(公告)日：2009-02-03

申请号：US11301322

申请日：2005-12-12

Applicant: Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

Inventor： Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Disclosed is a phase-changeable memory device and method of programming the same. The phase-changeable memory device includes memory cells each having multiple states, and a program pulse generator providing current pulses to the memory cells. The program pulse generator initializes a memory cell to a reset or set state by applying a first pulse thereto and thereafter provides a second pulse to program the memory cell to one of the multiple states. According to the invention, as a memory cell is programmed after being initialized to a reset or set state, it is possible to correctly program the memory cell without influence from the previous state of the memory cell.

Abstract translation: 公开了一种可变相存储器件及其编程方法。 相位可变存储器件包括各自具有多个状态的存储单元，以及向存储单元提供电流脉冲的编程脉冲发生器。 程序脉冲发生器通过向其施加第一个脉冲而将存储单元初始化为复位或置位状态，此后提供第二脉冲以将存储器单元编程为多个状态之一。 根据本发明，由于在初始化为复位或置位状态之后对存储单元进行编程，所以可以在不影响存储单元的先前状态的情况下正确编程存储单元。