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    DISTORTION CANCELLATION IN 3-D NON-VOLATILE MEMORY
    11.
    发明申请
    DISTORTION CANCELLATION IN 3-D NON-VOLATILE MEMORY 审中-公开
    三维非易失性存储器中的失败消除

    公开(公告)号：US20150332782A1

    公开(公告)日：2015-11-19

    申请号：US14811103

    申请日：2015-07-28

    Applicant: Apple Inc.

    Inventor： Eyal Gurgi ,  Micha Anholt ,  Yoav Kasorla

    IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26

    CPC classification number: G11C16/3427 ,  G06F3/0614 ,  G06F3/0653 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3431

    Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.

    Abstract translation: 包括以三维（3-D）配置排列的多个模拟存储器单元的存储器中的方法包括识别潜在地对一组目标存储器单元造成干扰的潜在干扰存储器单元的多个组。 估计由目标存储器单元上的潜在干扰存储器单元的相应组造成的部分失真分量。 逐渐积累部分失真分量，以产生影响目标存储器单元的估计复合失真，同时仅保留复合失真而不保留部分失真分量。 读取目标存储器单元，并且基于估计的复合失真来消除目标存储器单元中的干扰。

    ADVANCED PROGRAMMING VERIFICATION SCHEMES FOR MEMORY CELLS
    12.
    发明申请
    ADVANCED PROGRAMMING VERIFICATION SCHEMES FOR MEMORY CELLS 审中-公开
    用于记忆细胞的高级编程验证方案

    公开(公告)号：US20150193293A1

    公开(公告)日：2015-07-09

    申请号：US14662470

    申请日：2015-03-19

    Applicant: Apple Inc.

    Inventor： Eyal Gurgi ,  Yoav Kasorla ,  Barak Rotbard ,  Shai Ojalvo

    IPC: G06F11/07

    CPC classification number: G11C29/38 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/263 ,  G11C11/1677 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5678 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/12015 ,  G11C29/44 ,  G11C29/50012

    Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.

    Abstract translation: 一种用于数据存储的方法包括在存储器装置中接收用于存储在一组存储器单元中的数据。 通过执行程序和验证（P＆V）过程将数据存储在组中，该过程适用于组中的存储器单元的编程脉冲序列，并将组中的存储器单元的各自的模拟值与相应的验证阈值进行比较。 在P＆V进程成功完成之后，在存储器件中检测到存储的数据与接收到的数据之间的不匹配。 响应于不匹配报告数据存储错误。

    PROGRAMMABLE PEAK-CURRENT CONTROL IN NON-VOLATILE MEMORY DEVICES
    13.
    发明申请
    PROGRAMMABLE PEAK-CURRENT CONTROL IN NON-VOLATILE MEMORY DEVICES 有权
    非易失性存储器件中的可编程峰值电流控制

    公开(公告)号：US20150098272A1

    公开(公告)日：2015-04-09

    申请号：US14322102

    申请日：2014-07-02

    Applicant: Apple Inc.

    Inventor： Yoav Kasorla ,  Avraham Poza Meir

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3422

    Abstract: A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption.

    Abstract translation: 一种方法包括在存储器装置中接收指定存储器件不被超出的峰值功率消耗的命令。 存储器件的存储器根据命令中指定的峰值功耗进行配置。 在配置的存储器中执行数据存储操作，同时符合规定的峰值功耗。

    Mitigating reliability degradation of analog memory cells during long static and erased state retention
    18.
    发明授权
    Mitigating reliability degradation of analog memory cells during long static and erased state retention 有权
    在长静态和擦除状态保持期间，减轻模拟存储单元的可靠性降级

    公开(公告)号：US09236132B2

    公开(公告)日：2016-01-12

    申请号：US14249448

    申请日：2014-04-10

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

    IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

    Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

    Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。

    MITIGATION OF DATA RETENTION DRIFT BY PROGRAMMING NEIGHBORING MEMORY CELLS
    19.
    发明申请
    MITIGATION OF DATA RETENTION DRIFT BY PROGRAMMING NEIGHBORING MEMORY CELLS 审中-公开
    通过编程相邻存储器细胞来减缓数据保留

    公开(公告)号：US20150348632A1

    公开(公告)日：2015-12-03

    申请号：US14822992

    申请日：2015-08-11

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

    Abstract translation: 一种方法包括在共享公共隔离层并存储在公共隔离层中的代表数据值的电荷量的多个存储器单元中，分配用于数据存储的第一组存储器单元，以及分配第二组 用于保护存储在第一组中的电荷的存储单元不保持漂移。 数据存储在第一组的存储单元中。 防止第一组的存储单元中保持漂移的电荷的保护量被存储在第二组的存储单元中。

    Reliable readout of fuse data in an integrated circuit
    20.
    发明授权
    Reliable readout of fuse data in an integrated circuit 有权
    在集成电路中可靠读取熔丝数据

    公开(公告)号：US09136012B1

    公开(公告)日：2015-09-15

    申请号：US14269833

    申请日：2014-05-05

    Applicant: Apple Inc.

    Inventor： Yoav Kasorla ,  Shai Ojalvo ,  Eyal Gurgi

    IPC: G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G06F11/1044 ,  G11C17/16 ,  G11C29/74 ,  G11C29/787

    Abstract: An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.

    Abstract translation: 集成电路包括熔丝读出逻辑和第一和第二组保险丝。 其中一个集合包括一个或多个主熔丝，其燃烧状态表示相应的位值，并且这些组中的另一个包括一个或多个辅助熔丝，其燃烧状态指示存储在主熔丝中的位值。 熔丝读出逻辑被配置为通过感测主熔丝的燃烧状态来读取位值，并且通过感测一个或多个次熔丝的燃烧状态来有条件地校正读取位值。

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