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    System-In-Package Architecture with Wireless Bus Interconnect
    11.
    发明申请
    System-In-Package Architecture with Wireless Bus Interconnect 有权

    公开(公告)号：US20210149834A1

    公开(公告)日：2021-05-20

    申请号：US16685090

    申请日：2019-11-15

    Applicant: Arm Limited ,  ECS Partners Limited

    Inventor： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

    IPC: G06F13/40 ,  H04L12/40

    Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

    Devices and Methods to Store an Initialization State
    12.
    发明申请
    Devices and Methods to Store an Initialization State 有权

    公开(公告)号：US20210142839A1

    公开(公告)日：2021-05-13

    申请号：US16683192

    申请日：2019-11-13

    Applicant: Arm Limited

    Inventor： Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight

    IPC: G11C11/4072 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/22 ,  G11C7/10

    Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

    SMART SURFACE COVERING AND STRUCTURE HAVING REMOTELY INTERROGATABLE ANTENNA NODE ARRAY FOR REMOTE INTEGRITY CHECKING
    15.
    发明申请
    SMART SURFACE COVERING AND STRUCTURE HAVING REMOTELY INTERROGATABLE ANTENNA NODE ARRAY FOR REMOTE INTEGRITY CHECKING 审中-公开

    公开(公告)号：US20190163940A1

    公开(公告)日：2019-05-30

    申请号：US15825467

    申请日：2017-11-29

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  David Michael Bull ,  Edgar H. Callaway, JR.

    IPC: G06K7/10 ,  G06K7/00 ,  G01V1/00

    Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.

    Retention control in a memory device
    17.
    发明授权
    Retention control in a memory device 有权
    存储设备中的保留控制

    公开(公告)号：US09542994B1

    公开(公告)日：2017-01-10

    申请号：US14855068

    申请日：2015-09-15

    Applicant: ARM Limited

    Inventor： Pranay Prabhat ,  James Edward Myers

    IPC: G11C11/40 ,  G11C11/417 ,  G11C11/4072 ,  G11C11/413

    CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C5/148 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/413 ,  G11C11/418 ,  G11C2207/2227

    Abstract: A memory device and method of operating the memory device are provided. The memory device has bitcells arranged in a plurality of rows and columns. Row driver circuitry provides access to the array of bitcells by selection of an access row of the plurality of rows. The row driver circuitry comprises a retention control latch to store a retention control value and row power gating circuitry responsive to a retention signal to power gate at least one row when the retention control value has a first value and to leave the at least one row powered when the retention control value has a second value. Row-based retention of the content of the bit cells is thus provided, and the leakage current of the memory device when it is in a retention (e.g. sleep) mode, and only some of its rows contain valid data, can thus be reduced.

    Abstract translation: 提供了一种操作存储器件的存储器件和方法。 存储器件具有排列成多个行和列的位单元。 行驱动器电路通过选择多行的访问行来提供对位单元阵列的访问。 行驱动器电路包括保持控制锁存器，用于在保持控制值具有第一值时保存保持控制值和行电源门控电路，响应于保持信号对至少一行供电门，并且使至少一行动力 当保持控制值具有第二值时。 因此提供了位单元的内容的基于行的保持，并且因此可以减少存储器件处于保持（例如睡眠）模式时的泄漏电流，并且仅一些行包含有效数据。

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