公开(公告)号：US20230223255A1

公开(公告)日：2023-07-13

申请号：US18153272

申请日：2023-01-11

Applicant: ASM IP Holding, B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Dieter Pierreux ,  Kelly Houben ,  Rami Khazaka ,  Frederick Aryeetey ,  Peter Westrom ,  Omar Elleuch ,  Caleb Miskin

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68

CPC classification number: H01L21/0257 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/0262 ,  H01L21/02532

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

公开(公告)号：US11646204B2

公开(公告)日：2023-05-09

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230127177A1

公开(公告)日：2023-04-27

申请号：US18046637

申请日：2022-10-14

Applicant: ASM IP Holding B.V.

Inventor： Cornelis Thaddeus Herbschleb ,  Kelly Houben

IPC: C23C16/44 ,  H01L21/02 ,  C23C16/34 ,  C23C16/458

Abstract: A method for particle abatement in a semiconductor apparatus is provided. In a preferred embodiment, the method comprises processing a substrate in a process chamber of the semiconductor processing apparatus. The processing comprises loading the substrate in the process chamber having one or more inner surfaces, providing a reaction gas mixture to the process chamber, thereby forming a substrate film and a chamber wall film, and loading the substrate out of the process chamber. The method further comprises repeating the processing step one or more times until the chamber wall film has reached a pre-determined chamber wall film thickness, upon which exposing the inner surfaces to an ambient, thereby modifying at least an upper portion of the chamber wall film, thus reducing a probability of particle formation in the process chamber.

公开(公告)号：US11230766B2

公开(公告)日：2022-01-25

申请号：US15940729

申请日：2018-03-29

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Cornelis Thaddeus Herbschleb ,  Werner Knaepen ,  Bert Jongbloed ,  Steven Van Aerde ,  Kelly Houben ,  Theodorus Oosterlaken ,  Chris de Ridder ,  Lucian Jdira

IPC: C23C16/458 ,  C23C16/56 ,  C23C16/455 ,  C23C16/48 ,  C23C16/50 ,  C23C16/44

Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

公开(公告)号：US20210151315A1

公开(公告)日：2021-05-20

申请号：US17093224

申请日：2020-11-09

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Anna Trovato ,  Kelly Houben ,  Steven van Aerde ,  Bert Jongbloed ,  Wilco A. Verweij

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285

Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.

公开(公告)号：US10460932B2

公开(公告)日：2019-10-29

申请号：US15476702

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Steven R. A. Van Aerde ,  Kelly Houben ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.

公开(公告)号：US20190301014A1

公开(公告)日：2019-10-03

申请号：US15940729

申请日：2018-03-29

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Cornelis Thaddeus Herbschleb ,  Werner Knaepen ,  Bert Jongbloed ,  Steven Van Aerde ,  Kelly Houben ,  Theodorus Oosterlaken ,  Chris de Ridder ,  Lucian Jdira

IPC: C23C16/458 ,  C23C16/56 ,  C23C16/50 ,  C23C16/48 ,  C23C16/455

Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

公开(公告)号：US20180286679A1

公开(公告)日：2018-10-04

申请号：US15476752

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Kelly Houben ,  Steven R.A. Van Aerde ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/033

CPC classification number: H01L21/0337

Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

公开(公告)号：US20180286672A1

公开(公告)日：2018-10-04

申请号：US15476702

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Steven R.A. Van Aerde ,  Kelly Houben ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/306

Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.