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公开(公告)号：US10983440B2
公开(公告)日：2021-04-20
申请号：US16301458
申请日：2017-05-09
Applicant: ASML NETHERLANDS B.V.
Inventor： Jen-Shiang Wang , Jay Jianhui Chen
IPC: G03F7/20
Abstract: A method including: obtaining a relationship between a performance indicator of a substrate measurement recipe and a parameter of the substrate measurement recipe; deriving a range of the parameter from the relationship, wherein absolute values of the performance indicator satisfy a first condition or a magnitude of variation of the performance indicator satisfies a second condition, when the first parameter is in the range; selecting a substrate measurement recipe that has the parameter in the range; and inspecting a substrate with the selected substrate measurement recipe.
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公开(公告)号：US10691029B2
公开(公告)日：2020-06-23
申请号：US16305913
申请日：2017-06-01
Applicant: ASML NETHERLANDS B.V.
Inventor： Ning Gu , Daimian Wang , Jen-Shiang Wang
Abstract: A method including computing a multi-variable cost function, the multi-variable cost function representing a metric characterizing a degree of matching between a result when measuring a metrology target structure using a substrate measurement recipe and a behavior of a pattern of a functional device, the metric being a function of a plurality of design variables including a parameter of the metrology target structure, and adjusting the design variables and computing the cost function with the adjusted design variables, until a certain termination condition is satisfied.
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公开(公告)号：US09494874B2
公开(公告)日：2016-11-15
申请号：US14578036
申请日：2014-12-19
Applicant: ASML NETHERLANDS B.V.
Inventor： Guangqing Chen , Jen-Shiang Wang , Shufeng Bai
CPC classification number: G03F7/70633 , G03F7/705 , G03F7/70625 , G03F7/70641 , G03F7/70683
Abstract: A system to, and a method to, select a metrology target for use on a substrate including performing a lithographic simulation for a plurality of points on a process window region for each proposed target, identifying a catastrophic error for any of the plurality of points for each proposed target, eliminating each target having a catastrophic error at any of the plurality of points, performing a metrology simulation to determine a parameter over the process window for each target not having a catastrophic error at any of the plurality of points, and using the one or more resulting determined simulated parameters to evaluate target quality.
Abstract translation: 一种用于选择在基板上使用的测量目标的系统和方法，包括对于每个所提出的目标执行对于处理窗口区域上的多个点的光刻模拟，识别多个点中的任一点的灾难性误差 每个所提出的目标，消除每个目标在多个点中的任一点具有灾难性错误，执行度量仿真以确定在多个点中的任一点上没有灾难性错误的每个目标的处理窗口上的参数，并且使用 一个或多个产生的确定的模拟参数来评估目标质量。
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公开(公告)号：US20150186581A1
公开(公告)日：2015-07-02
申请号：US14577820
申请日：2014-12-19
Applicant: ASML NETHERLANDS B.V.
Inventor： Guangqing Chen , Eric Richard Kent , Jen-Shiang Wang , Omer Abubaker Omer Adam
IPC: G06F17/50
CPC classification number: G03F7/706 , G03F7/70625 , G03F7/70633 , G03F7/70641 , G03F7/70683 , G06F17/5009 , G06F17/5068 , G06F2217/12 , G06F2217/14
Abstract: A method of metrology target design is described. The method includes determining a sensitivity of a parameter for a metrology target design to an optical aberration, determining the parameter for a product design exposed using an optical system of a lithographic apparatus, and determining an impact on the parameter of the metrology target design based on the parameter for the product design and the product of the sensitivity and one or more of the respective aberrations of the optical system.
Abstract translation: 描述了一种计量目标设计方法。 该方法包括确定用于度量目标设计的参数对光学像差的灵敏度，确定使用光刻设备的光学系统暴露的产品设计的参数，以及基于以下方式确定对度量目标设计的参数的影响： 产品设计的参数和灵敏度的乘积以及光学系统的各个像差中的一个或多个。
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公开(公告)号：US11977336B2
公开(公告)日：2024-05-07
申请号：US17059771
申请日：2019-05-14
Applicant: ASML NETHERLANDS B.V.
Inventor： Jen-Shiang Wang , Qian Zhao , Yunbo Guo , Yen-Wen Lu , Mu Feng , Qiang Zhang
IPC: G03F7/00
CPC classification number: G03F7/705 , G03F7/70441 , G03F7/70625 , G03F7/70655 , G03F7/706837
Abstract: A method for improving a process model for a patterning process, the method including obtaining a) a measured contour from an image capture device, and b) a simulated contour generated from a simulation of the process model. The method also includes aligning the measured contour with the simulated contour by determining an offset between the measured contour and the simulated contour. The process model is calibrated to reduce a difference, computed based on the determined offset, between the simulated contour and the measured contour.
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Patent Agency Ranking
公开(公告)号：US11875101B2
公开(公告)日：2024-01-16
申请号：US17616368
申请日：2020-05-25
Applicant: ASML NETHERLANDS B.V.
Inventor： Jen-Shiang Wang , Feng Chen , Matteo Alessandro Francavilla , Jan Wouter Bijlsma
IPC: G06F30/30 , G06F30/398 , G03F7/00 , G06F30/392 , G06F30/27 , G06F119/18
CPC classification number: G06F30/398 , G03F7/705 , G06F30/27 , G06F30/392 , G06F2119/18
Abstract: A patterning process modeling method includes determining, with a front end of a process model, a function associated with process physics and/or chemistry of an operation within a patterning process flow; and determining, with a back end of the process model, a predicted wafer geometry. The back end includes a volumetric representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volumetric representation of the wafer. The volumetric representation of the wafer may be generated using volumetric dynamic B-trees. The volumetric representation of the wafer may be manipulated using a level set method. The function associated with the process physics and/or chemistry of the operation within the patterning process flow may be a velocity/speed function. Incoming flux on a modeled surface of the wafer may be determined using ray tracing.
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公开(公告)号：US11675274B2
公开(公告)日：2023-06-13
申请号：US16484582
申请日：2018-02-21
Applicant: ASML NETHERLANDS B.V.
Inventor： Yongfa Fan , Leiwu Zheng , Mu Feng , Qian Zhao , Jen-Shiang Wang
CPC classification number: G03F7/705 , G03F1/80 , G03F7/70625 , H01L22/34
Abstract: A method involving determining an etch bias for a pattern to be etched using an etch step of a patterning process based on an etch bias model, the etch bias model including a formula having a variable associated with a spatial property of the pattern or with an etch plasma species concentration of the etch step, and including a mathematical term including a natural exponential function to the power of a parameter that is fitted or based on an etch time of the etch step; and adjusting the patterning process based on the determined etch bias.
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公开(公告)号：US11614690B2
公开(公告)日：2023-03-28
申请号：US16478489
申请日：2018-01-24
Applicant: ASML NETHERLANDS B.V.
Inventor： Mu Feng , Mir Farrokh Shayegan Salek , Dianwen Zhu , Leiwu Zheng , Rafael C. Howell , Jen-Shiang Wang
IPC: G05B19/418 , G03F7/20
Abstract: Methods of constructing a process model for simulating a characteristic of a product of lithography from patterns produced under different processing conditions. The methods use a deviation between the variation of the simulated characteristic and the variation of the measured characteristic to adjust a parameter of the process model.
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公开(公告)号：US20210271172A1
公开(公告)日：2021-09-02
申请号：US17176559
申请日：2021-02-16
Applicant: ASML NETHERLANDS B.V.
Inventor： Ya Luo , Yu Cao , Jen-Shiang Wang , Yen-Wen Lu
Abstract: Methods of determining, and using, a process model that is a machine learning model. The process model is trained partially based on simulation or based on a non-machine learning model. The training data may include inputs obtained from a design layout, patterning process measurements, and image measurements.
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公开(公告)号：US10296681B2
公开(公告)日：2019-05-21
申请号：US15982933
申请日：2018-05-17
Applicant: ASML NETHERLANDS B.V.
Inventor： Guangqing Chen , Shufeng Bai , Eric Richard Kent , Yen-Wen Lu , Paul Anthony Tuffy , Jen-Shiang Wang , Youping Zhang , Gertjan Zwartjes , Jan Wouter Bijlsma
Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
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