公开(公告)号：US20140181467A1

公开(公告)日：2014-06-26

申请号：US13725063

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

IPC: G06F15/80

CPC classification number: G06F9/3887 ,  G06F9/30036

Abstract: Methods, and media, and computer systems are provided. The method includes, the media includes control logic for, and the computer system includes a processor with control logic for overriding an execution mask of SIMD hardware to enable at least one of a plurality of lanes of the SIMD hardware. Overriding the execution mask is responsive to a data parallel computation and a diverged control flow of a workgroup.

Abstract translation: 提供了方法，媒体和计算机系统。 该方法包括：媒体包括用于的控制逻辑，并且计算机系统包括具有用于覆盖SIMD硬件的执行掩码的控制逻辑的处理器，以使能SIMD硬件的多个通道中的至少一个。 覆盖执行掩码响应于数据并行计算和工作组的分散控制流。

公开(公告)号：US20140173210A1

公开(公告)日：2014-06-19

申请号：US13719730

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James O'Connor ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0815

Abstract: A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.

Abstract translation: 提供了一种有助于高速缓存一致性策略的数据处理设备。 在一个实施例中，数据处理设备利用与处理引擎相关联的高速缓存的无效标签。 在一些实施例中，高速缓存被配置为存储多个高速缓存条目，其中每个高速缓存条目包括被配置为存储数据的高速缓存行和被配置为存储与存储在高速缓存行中的数据相关联的地址信息的对应高速缓存标签。 这样的地址信息包括关于存储在高速缓存标签中的地址的无效标志。 每个缓存标签与被配置为存储与存储在高速缓存标签中的地址的无效命令相关的信息的无效标签相关联。 在这种实施例中，高速缓存被配置为基于存储在相应无效标签中的信息来设置高速缓存标签的无效标志。

公开(公告)号：US20140149710A1

公开(公告)日：2014-05-29

申请号：US13689421

申请日：2012-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

IPC: G06F12/02

CPC classification number: G06F9/3887 ,  G06F9/3851

Abstract: Methods, media, and computing systems are provided. The method includes, the media are configured for, and the computing system includes a processor with control logic for allocating memory for storing a plurality of local register states for work items to be executed in single instruction multiple data hardware and for repacking wavefronts that include work items associated with a program instruction responsive to a conditional statement. The repacking is configured to create repacked wavefronts that include at least one of a wavefront containing work items that all pass the conditional statement and a wavefront containing work items that all fail the conditional statement.

Abstract translation: 提供了方法，媒体和计算系统。 该方法包括：媒体被配置用于计算系统，并且计算系统包括具有控制逻辑的处理器，该控制逻辑用于分配存储器，用于存储要在单指令多数据硬件中执行的工作项的多个本地寄存器状态，以及用于重新包装工作的波前 与响应于条件语句的程序指令相关联的项目。 重新配置被配置为创建重新包装的波前，其包括包含工作项的波前中的至少一个，所述工作项全部通过条件语句，以及包含所有未完成条件语句的工作项的波阵面。

公开(公告)号：US12190174B2

公开(公告)日：2025-01-07

申请号：US16425881

申请日：2019-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Sergey Blagodurov ,  Anthony T. Gutierrez ,  Matthew D. Sinclair ,  David A. Wood ,  Bradford M. Beckmann

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait instruction is part of a mutual exclusion synchronization primitive and is detected by determining that there is a low number of updates to the condition variable prior to detecting that the condition has been met. In a high contention scenario, the workgroup scheduler wakes up one workgroup and schedules another workgroup to be woken up at a time in the future. In a non-contention scenario, more than one workgroup can be woken up at the same time.

公开(公告)号：US10522193B2

公开(公告)日：2019-12-31

申请号：US16129252

申请日：2018-09-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  Bradford M. Beckmann ,  James M. O'Connor ,  Lisa R. Hsu

IPC: G06F12/00 ,  G11C5/06 ,  G06F12/02 ,  G06F12/10 ,  G06F13/16 ,  G11C7/10

Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.

公开(公告)号：US10019377B2

公开(公告)日：2018-07-10

申请号：US15162464

申请日：2016-05-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Bradford M. Beckmann ,  Shuai Che ,  Sooraj Puthoor

IPC: G06F12/1009 ,  G06F12/0837 ,  G06F12/14 ,  G06F12/0817 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/1027 ,  G06F12/1483 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/621 ,  G06F2212/657 ,  Y02D10/13

Abstract: The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.

公开(公告)号：US09804883B2

公开(公告)日：2017-10-31

申请号：US14542042

申请日：2014-11-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Marc S. Orr ,  Bradford M. Beckmann ,  Ayse Yilmazer ,  Shuai Che ,  David A. Wood ,  Mark D. Hill

IPC: G06F9/46 ,  G06F12/0806 ,  G06F3/06 ,  G06F12/0871

CPC classification number: G06F9/46 ,  G06F3/06 ,  G06F12/0806 ,  G06F12/0871 ,  G06F2212/222 ,  G06F2212/313 ,  G06F2212/401

Abstract: Described herein is an apparatus and method for remote scoped synchronization, which is a new semantic that allows a work-item to order memory accesses with a scope instance outside of its scope hierarchy. More precisely, remote synchronization expands visibility at a particular scope to all scope-instances encompassed by that scope. Remote scoped synchronization operation allows smaller scopes to be used more frequently and defers added cost to only when larger scoped synchronization is required. This enables programmers to optimize the scope that memory operations are performed at for important communication patterns like work stealing. Executing memory operations at the optimum scope reduces both execution time and energy. In particular, remote synchronization allows a work-item to communicate with a scope that it otherwise would not be able to access. Specifically, work-items can pull valid data from and push updates to scopes that do not (hierarchically) contain them.

公开(公告)号：US09766936B2

公开(公告)日：2017-09-19

申请号：US14935056

申请日：2015-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

公开(公告)号：US09411663B2

公开(公告)日：2016-08-09

申请号：US13782117

申请日：2013-03-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven K. Reinhardt ,  Marc S. Orr ,  Bradford M. Beckmann

IPC: G06F9/54 ,  G06F1/32 ,  G06F12/08

CPC classification number: G06F9/542 ,  G06F1/32 ,  G06F1/3206 ,  G06F12/0811 ,  G06F12/0824 ,  G06F12/0897

Abstract: The described embodiments comprise a first hardware context. The first hardware context receives, from a second hardware context, an indication of a memory location and a condition to be met by the memory location. The first hardware context then sends a signal to the second hardware context when the memory location meets the condition.

Abstract translation: 所描述的实施例包括第一硬件上下文。 第一硬件上下文从第二硬件上下文接收存储器位置的指示和存储器位置要满足的条件。 当存储器位置满足条件时，第一硬件上下文然后向第二硬件上下文发送信号。

公开(公告)号：US09361118B2

公开(公告)日：2016-06-07

申请号：US14275271

申请日：2014-05-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Derek R. Hower ,  Mark D. Hill ,  David Wood ,  Steven K. Reinhardt ,  Benedict R. Gaster ,  Blake A. Hechtman ,  Bradford M. Beckmann

IPC: G06F12/00 ,  G06F9/44 ,  G06F9/52

CPC classification number: G06F9/44 ,  G06F8/436 ,  G06F8/454 ,  G06F9/52 ,  G06F9/522 ,  G06F9/524 ,  G06F9/526

Abstract: A method, computer program product, and system is described that determines the correctness of using memory operations in a computing device with heterogeneous computer components. Embodiments include an optimizer based on the characteristics of a Sequential Consistency for Heterogeneous-Race-Free (SC for HRF) model that analyzes a program and determines the correctness of the ordering of events in the program. HRF models include combinations of the properties: scope order, scope inclusion, and scope transitivity. The optimizer can determine when a program is heterogeneous-race-free in accordance with an SC for HRF memory consistency model. For example, the optimizer can analyze a portion of program code, respect the properties of the SC for HRF model, and determine whether a value produced by a store memory event will be a candidate for a value observed by a load memory event. In addition, the optimizer can determine whether reordering of events is possible.

Abstract translation: 描述了一种方法，计算机程序产品和系统，其确定在具有异构计算机组件的计算设备中使用存储器操作的正确性。 实施例包括基于用于异构无竞争（SC for HRF）的顺序一致性的特性的优化器，该模型分析程序并确定程序中的事件的顺序的正确性。 HRF模型包括属性的组合：范围顺序，范围包含和范围传递性。 优化器可以根据HR对HRF内存一致性模型的SC来确定程序何时是异构无竞争的。 例如，优化器可以分析程序代码的一部分，尊重SC的HRF模型的属性，并且确定由存储器存储器事件产生的值是否将是由加载存储器事件观察到的值的候选。 此外，优化器可以确定是否可能重新排序事件。