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公开(公告)号：US11137809B2
公开(公告)日：2021-10-05
申请号：US16228036
申请日：2018-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Karthik Rao , Wei Huang , Xudong An , Manish Arora , Joseph L. Greathouse
Abstract: A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.
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公开(公告)号：US20170185409A1
公开(公告)日：2017-06-29
申请号：US14981310
申请日：2015-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Leonardo de Paula Rosa Piga , Abhinandan Majumdar , Indrani Paul , Wei Huang , Manish Arora , Joseph L. Greathouse
IPC: G06F9/30
CPC classification number: G06F9/30192 , G06F9/30014 , G06F9/30083 , G06F9/30145 , G06F11/00
Abstract: Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.
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13.发明申请公开(公告)号：US20160034023A1
公开(公告)日：2016-02-04
申请号：US14448096
申请日：2014-07-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Manish ARORA , Indrani Paul , Yasuko Eckert , Joseph L. Greathouse , Srilatha Manne
CPC classification number: G06F1/3275 , G06F1/3206 , G06F12/0811 , G06F12/0862 , G06F2212/1016 , G06F2212/502 , Y02D10/14
Abstract: A system may determine that a processor has powered up. The system may determine a first prefetching policy based on determining that the processor has powered up. The system may fetch information, from a main memory and for storage by a cache associated with the processor, using the first prefetching policy. The system may determine, after fetching information using the first prefetching policy, to apply a second prefetching policy that is different than the first prefetching policy. The system may fetch information, from the main memory and for storage by the cache, using the second prefetching policy.
Abstract translation: 系统可以确定处理器已经通电。 该系统可以基于确定处理器通电来确定第一预取策略。 系统可以使用第一预取策略从主存储器获取信息，并且由与处理器相关联的高速缓存存储信息。 在使用第一预取策略获取信息之后，系统可以确定应用与第一预取策略不同的第二预取策略。 系统可以使用第二预取策略从主存储器获取信息并由高速缓存存储。
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公开(公告)号：US20240330046A1
公开(公告)日：2024-10-03
申请号：US18374837
申请日：2023-09-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Alexander Fuad Ashkar , Joseph L. Greathouse , Manu Rastogi
CPC classification number: G06F9/4881 , G06F9/5038 , G06F2209/5021
Abstract: A processing device includes a hardware scheduler, an unmapped queue unit, and command processor, and a plurality of compute units. Responsive to a queue doorbell being an unmapped queue doorbell, the unmapped queue unit is configured to transmit a signal to the hardware scheduler indicating work has been placed into a queue currently unmapped to a hardware queue of the processing device. The hardware scheduler is configured to map the queue to a hardware queue of a plurality of hardware queues at the processing device in response to the signal. The command processor is configured to dispatch the work associated with the mapped queue to one or more compute units of the plurality of compute units.
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公开(公告)号：US11853734B2
公开(公告)日：2023-12-26
申请号：US17740828
申请日：2022-05-10
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gregory P. Rodgers , Joseph L. Greathouse
CPC classification number: G06F8/4435 , G06F17/16
Abstract: A processing system includes a compiler that automatically identifies sequences of instructions of tileable source code that can be replaced with tensor operations. The compiler generates enhanced code that replaces the identified sequences of instructions with tensor operations that invoke a special-purpose hardware accelerator. By automatically replacing instructions with tensor operations that invoke the special-purpose hardware accelerator, the compiler makes the performance improvements achievable through the special-purpose hardware accelerator available to programmers using high-level programming languages.
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Patent Agency Ranking
公开(公告)号：US11347486B2
公开(公告)日：2022-05-31
申请号：US16832275
申请日：2020-03-27
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gregory P. Rodgers , Joseph L. Greathouse
Abstract: A processing system includes a compiler that automatically identifies sequences of instructions of tileable source code that can be replaced with tensor operations. The compiler generates enhanced code that replaces the identified sequences of instructions with tensor operations that invoke a special-purpose hardware accelerator. By automatically replacing instructions with tensor operations that invoke the special-purpose hardware accelerator, the compiler makes the performance improvements achievable through the special-purpose hardware accelerator available to programmers using high-level programming languages.
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公开(公告)号：US10713059B2
公开(公告)日：2020-07-14
申请号：US14490213
申请日：2014-09-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Joseph L. Greathouse , Mitesh R. Meswani , Sooraj Puthoor , Dmitri Yudanov , James M. O'Connor
IPC: G06F9/38
Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.
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公开(公告)号：US20180069767A1
公开(公告)日：2018-03-08
申请号：US15257286
申请日：2016-09-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Arkaprava Basu , Joseph L. Greathouse , Guru Prasadh V. Venkataramani , Jan Vesely
IPC: H04L12/24 , H04L29/08 , G06F12/0817 , G06F9/50
CPC classification number: G06F12/0828 , G06F9/5011 , G06F9/5083 , G06F2209/504
Abstract: Techniques described herein improve processor performance in situations where a large number of system service requests are being received from other devices. More specifically, upon detecting that certain operating conditions that indicate a processor slowdown are present, the processor performs one or more system service adjustment techniques. These techniques include throttling (reducing the rate of handling) of such requests, coalescing (grouping multiple requests into a single group) the requests, disabling microarchitctural structures (such as caches or branch prediction units) or updates to those structures, and prefetching data for or pre-performing these requests. Each of these adjustment techniques helps to reduce the number of and/or workload associated with servicing requests for system services.
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公开(公告)号：US09483379B2
公开(公告)日：2016-11-01
申请号：US14054356
申请日：2013-10-15
Applicant: Advanced Micro Devices, Inc.
Inventor： Joseph L. Greathouse , David S. Christie
CPC classification number: G06F11/36 , G06F11/3065 , G06F11/3072 , G06F11/3093 , G06F11/3466 , G06F11/3471 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F2201/81 , G06F2201/865 , G06F2201/88
Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. The processor allocates a memory region for the purpose of creating “random branches” in the computer code utilizing existing memory access instructions. When the processor processes a given instruction, the processor both accesses a first location in the memory region and may determine a condition is satisfied. In response, the processor generates an interrupt. The corresponding interrupt handler may transfer control flow from the computer program to instrumentation code. The condition may include a pointer storing an address pointing to locations within the memory region equals a given address after the point is updated. Alternatively, the condition may include an updated data value stored in a location pointed to by the given address equals a threshold value.
Abstract translation: 一种有效执行程序仪表的系统和方法。 处理器处理存储在存储器中的指令。 处理器为了在现有的存储器访问指令中的计算机代码中创建“随机分支”而分配存储器区域。 当处理器处理给定的指令时，处理器都访问存储器区域中的第一位置并且可以确定满足条件。 作为响应，处理器产生中断。 相应的中断处理程序可以将控制流程从计算机程序传送到仪表代码。 条件可以包括存储指向存储器区域内的位置的地址的指针等于点更新之后的给定地址。 或者，条件可以包括存储在由给定地址指向的位置的更新的数据值等于阈值。
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公开(公告)号：US20160085551A1
公开(公告)日：2016-03-24
申请号：US14490213
申请日：2014-09-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Joseph L. Greathouse , Mitesh R. Meswani , Sooraj Puthoor , Dmitri Yudanov , James M. O'Connor
CPC classification number: G06F9/3887 , G06F9/3851
Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.
Abstract translation: 呈现并行执行多个线程的计算单元。 计算单元包括一个或多个单指令多数据（SIMD）单元和读取和解码逻辑。 SIMD单元具有不同数量的算术逻辑单元（ALU），使得每个SIMD单元可以执行不同数量的线程。 获取和解码逻辑与每个SIMD单元通信，并且被配置为基于这样不同数量的ALU将线程分配给SIMD单元以供执行。
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