公开(公告)号：US09953687B1

公开(公告)日：2018-04-24

申请号：US15299709

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Ryan Freese ,  Russell J. Schreiber

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/12 ,  H03K19/0185 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/222 ,  G11C7/225 ,  H03K19/00323 ,  H03K19/018507

Abstract: An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.

公开(公告)号：US11715514B2

公开(公告)日：2023-08-01

申请号：US17359209

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4074 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C11/4096 ,  G11C7/106 ,  G11C7/1009 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4085 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.

公开(公告)号：US20230071807A1

公开(公告)日：2023-03-09

申请号：US17984796

申请日：2022-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US20220359015A1

公开(公告)日：2022-11-10

申请号：US17359209

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/08 ,  G11C7/10

Abstract: A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.

公开(公告)号：US20220206948A1

公开(公告)日：2022-06-30

申请号：US17699401

申请日：2022-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber

IPC: G06F12/0877 ,  G06F12/06 ,  G11C7/10 ,  G11C8/12 ,  G06F12/02

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

公开(公告)号：US10541013B1

公开(公告)日：2020-01-21

申请号：US16189185

申请日：2018-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Tawfik Ahmed ,  Ilango Jeyasubramanian

IPC: G11C8/18 ,  G11C8/08 ,  G11C11/408 ,  G11C11/418

Abstract: A word line driver circuit receives a word line input signal and supplies a word line driver output signal to a worldline. The word line driver circuit includes a transistor having a first current carrying terminal coupled to the word line driver output signal and a second current carrying terminal coupled to a first node. A gate of the transistor is coupled to the word line input signal, and the transistor provides a path from the word line to the first node while the word line is asserted. A programmable word line underdrive circuit is coupled between the first node and a ground node to reduce a voltage on the word line output signal. A plurality of word line driver circuits are coupled to the first node and use the word line underdrive circuit to underdrive their respective word lines.

公开(公告)号：US12066948B2

公开(公告)日：2024-08-20

申请号：US17699401

申请日：2022-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0877 ,  G11C7/10 ,  G11C8/12

CPC classification number: G06F12/0877 ,  G06F12/0246 ,  G06F12/0661 ,  G11C7/1045 ,  G11C8/12

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

公开(公告)号：US20230100607A1

公开(公告)日：2023-03-30

申请号：US17488519

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu ,  Keith A. Kasprak

IPC: G11C11/419

Abstract: A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

公开(公告)号：US11610627B2

公开(公告)日：2023-03-21

申请号：US17359254

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4074

Abstract: A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

公开(公告)号：US20220415386A1

公开(公告)日：2022-12-29

申请号：US17358527

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Tawfik Ahmed ,  Andrew J. Robison ,  Russell J. Schreiber

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.