公开(公告)号：US20240321827A1

公开(公告)日：2024-09-26

申请号：US18474158

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Omar Zia ,  Thomas D Burd ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Srividhya Venkataraman ,  Yan Wang ,  John Wuu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321668A1

公开(公告)日：2024-09-26

申请号：US18474138

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Thomas D. Burd ,  Gabriel H. Loh ,  John Wuu ,  Kevin Gillespie ,  Raja Swaminathan ,  Richard Schultz ,  Samuel Naffziger ,  Srividhya Venkataraman ,  Yan Wang

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/34 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1437

Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240193844A1

公开(公告)日：2024-06-13

申请号：US18077424

申请日：2022-12-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Fowler ,  Samuel Naffziger ,  Michael Mantor ,  Mark Leather

IPC: G06T15/00 ,  G06F9/38

CPC classification number: G06T15/005 ,  G06F9/3802

Abstract: A graphics processing unit (GPU) of a processing system is partitioned into multiple dies (referred to as GPU chiplets) that are configurable to collectively function and interface with an application as a single GPU in a first mode and as multiple GPUs in a second mode. By dividing the GPU into multiple GPU chiplets, the processing system flexibly and cost-effectively configures an amount of active GPU physical resources based on an operating mode. In addition, a configurable number of GPU chiplets are assembled into a single GPU, such that multiple different GPUs having different numbers of GPU chiplets can be assembled using a small number of tape-outs and a multiple-die GPU can be constructed out of GPU chiplets that implement varying generations of technology.

公开(公告)号：US20190393123A1

公开(公告)日：2019-12-26

申请号：US16563077

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20190268086A1

公开(公告)日：2019-08-29

申请号：US15903253

申请日：2018-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Michael K. Ciraula ,  Russell Schreiber

IPC: H04J99/00 ,  H01L23/48 ,  H01L23/00

Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

公开(公告)号：US20150106642A1

公开(公告)日：2015-04-16

申请号：US14053315

申请日：2013-10-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Naffziger ,  Baomin Liu ,  Maxat Touzelbaev

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

Abstract: An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.

Abstract translation: 集成电路包括多个处理器核和系统管理单元。 多个处理器核心各自以多个性能状态中的一个操作。 系统管理单元耦合到多个处理器核心，用于设置多个处理器核心的性能状态。 系统管理单元基于从估计的功耗计算出的第一温度和基于温度测量的第二温度来提高多个处理器核心的第一处理器核心的第一性能状态。

公开(公告)号：US20240321706A1

公开(公告)日：2024-09-26

申请号：US18474151

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： William George En ,  Samuel Naffziger ,  Regina T. Schmidt ,  Omar Zia ,  John Wuu

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11164807B2

公开(公告)日：2021-11-02

申请号：US16563077

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US10452554B2

公开(公告)日：2019-10-22

申请号：US15094391

申请日：2016-04-08

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ihab Amer ,  Khaled Mammou ,  Haibo Liu ,  Edward Harold ,  Fabio Gulino ,  Samuel Naffziger ,  Gabor Sines ,  Lawrence A. Bair ,  Andy Sung ,  Lei Zhang

IPC: G06F12/08 ,  G11C11/417 ,  G06F12/0877 ,  G06F12/0893 ,  G11C5/14

Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

公开(公告)号：US20180364782A1

公开(公告)日：2018-12-20

申请号：US16011476

申请日：2018-06-18

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Leonardo De Paula Rosa Piga ,  Samuel Naffziger ,  Ivan Matosevic ,  Indrani Paul

IPC: G06F1/32

Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.