公开(公告)号：US20190214323A1

公开(公告)日：2019-07-11

申请号：US16354049

申请日：2019-03-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH ,  Hong-Ping LIN ,  Dao-Long CHEN ,  Ping-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/29 ,  C08G59/42 ,  C08K5/5435 ,  C08K5/544 ,  C08K3/04 ,  C08K3/36 ,  H01L23/00 ,  C09D163/00

CPC classification number: H01L23/295 ,  C08G59/42 ,  C08K3/04 ,  C08K3/36 ,  C08K5/5435 ,  C08K5/544 ,  C09D163/00 ,  H01L21/563 ,  H01L23/296 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a filler composition, wherein the filler composition includes particles each including both carbon and silica, wherein the filler composition is substantially devoid of alumina or silicon carbide, and the filler composition has a weight ratio of carbon to silica of at least greater than 1.0.

公开(公告)号：US20170141007A1

公开(公告)日：2017-05-18

申请号：US14943519

申请日：2015-11-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH ,  Hong-Ping LIN ,  Dao-Long CHEN ,  Ping-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/29 ,  H01L23/00 ,  C08K3/36 ,  C09D163/00 ,  C08K3/04

CPC classification number: H01L23/295 ,  C08G59/42 ,  C08K3/04 ,  C08K3/36 ,  C08K5/5435 ,  C08K5/544 ,  C09D163/00 ,  H01L21/563 ,  H01L23/296 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure relates to a filler composition for a semiconductor package. The filler composition comprises carbon and silica.

公开(公告)号：US20250157947A1

公开(公告)日：2025-05-15

申请号：US19021138

申请日：2025-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung HUANG ,  Meng-Kai SHIH ,  Wei-Hong LAI ,  Wei Chu SUN

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/66 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/552

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

公开(公告)号：US20210134696A1

公开(公告)日：2021-05-06

申请号：US16676284

申请日：2019-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Meng-Kai SHIH ,  Chih-Pin HUNG

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/427 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, an electronic component disposed on the substrate, a supporting structure disposed on the substrate and surrounding the electronic component, and a heat spreading structure disposed on the supporting structure. A length of the supporting structure and a length of the heat spreading structure are greater than a length of the substrate.

公开(公告)号：US20210074676A1

公开(公告)日：2021-03-11

申请号：US16563716

申请日：2019-09-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20200279814A1

公开(公告)日：2020-09-03

申请号：US16289067

申请日：2019-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung HUANG ,  Meng-Kai SHIH ,  Wei-Hong LAI ,  Wei Chu SUN

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/552 ,  H01L23/31 ,  H01L21/48 ,  H01L21/66

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

公开(公告)号：US20200066612A1

公开(公告)日：2020-02-27

申请号：US16112248

申请日：2018-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Tang-Yuan CHEN ,  Jin-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.

公开(公告)号：US20180358237A1

公开(公告)日：2018-12-13

申请号：US15619413

申请日：2017-06-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Xu LU ,  Tang-Yuan CHEN ,  Jin-Yuan LAI ,  Tse-Chuan CHOU ,  Meng-Kai SHIH ,  Shin-Lih TARNG

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate. A distance between the second surface of the substrate and an extension of the second surface of the semiconductor device on the first surface of the substrate is less than or equal to twice a distance between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate extends along at least three sides of the semiconductor device.