公开(公告)号：US20190074264A1

公开(公告)日：2019-03-07

申请号：US15698451

申请日：2017-09-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/81

Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.

公开(公告)号：US20190287947A1

公开(公告)日：2019-09-19

申请号：US16434008

申请日：2019-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/538

Abstract: A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.

公开(公告)号：US20190164859A1

公开(公告)日：2019-05-30

申请号：US15823467

申请日：2017-11-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tsan-Hsien CHEN ,  Ian HU ,  Jin-Feng YANG ,  Shih-Wei CHEN ,  Hui-Chen HSU

IPC: H01L23/31 ,  H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/3128 ,  H01L21/4814 ,  H01L21/565 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/1134 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package device includes a substrate, an electronic component, a bonding wire, a heat spreader, a thermal conductive structure and an encapsulant. The electronic component is disposed on the substrate. The bonding wire connects the electronic component to the substrate. The heat spreader is disposed over the electronic component. The thermal conductive structure is disposed between the heat spreader and the electronic component. The thermal conductive structure includes two polymeric layers and a thermal conductive layer. The conductive layer is disposed between the two polymeric layers. The thermal conductive layer has a first end in contact with the electronic component and a second end in contact with the heat spreader. The encapsulant covers the bonding wire.

公开(公告)号：US20220084926A1

公开(公告)日：2022-03-17

申请号：US17018701

申请日：2020-09-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Jin-Feng YANG ,  Cheng-Yu TSAI ,  Hung-Hsien HUANG

IPC: H01L23/498 ,  H01L23/427 ,  H01L23/00 ,  H01L21/48

Abstract: A substrate structure, a method for manufacturing the same and a semiconductor device structure including the same are provided. The substrate structure includes a heat pipe, a first conductive layer and an insulation layer. The heat pipe has an upper surface and a lower surface. The heat pipe includes an opening extending from the upper surface to the lower surface. The first conductive layer is disposed on the upper surface and includes a via structure passing through the opening. The insulation layer is disposed between the heat pipe and the conductive layer.

公开(公告)号：US20180226320A1

公开(公告)日：2018-08-09

申请号：US15429024

申请日：2017-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Jia-Rung HO ,  Jin-Feng YANG ,  Chih-Pin HUNG ,  Ping-Feng YANG

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/373 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83493 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15321 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/29099

Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.

公开(公告)号：US20200091036A1

公开(公告)日：2020-03-19

申请号：US16566495

申请日：2019-09-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsin-En CHEN ,  Ian HU ,  Jin-Feng YANG

IPC: H01L23/427 ,  H01L23/00

Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, a vapor chamber and a heat dissipating device. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The vapor chamber is thermally connected to a first surface of the semiconductor die. The vapor chamber defines an enclosed chamber for accommodating a first working liquid. The heat dissipating device is thermally connected to the vapor chamber. The heat dissipating device defines a substantially enclosed space for accommodating a second working liquid.

公开(公告)号：US20200066612A1

公开(公告)日：2020-02-27

申请号：US16112248

申请日：2018-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Tang-Yuan CHEN ,  Jin-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.