公开(公告)号：US20160211235A1

公开(公告)日：2016-07-21

申请号：US14599366

申请日：2015-01-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long CHEN ,  Ping-Feng YANG ,  Chang-Chi LEE ,  Chien-Fan CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0614 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1414 ,  H01L2224/16055 ,  H01L2224/16056 ,  H01L2224/81191 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

Abstract translation: 本公开涉及凸块结构以及具有该凸块结构的半导体器件和半导体器件封装。 半导体器件包括主体，至少一个导电金属焊盘和至少一个金属支柱。 身体包括第一表面。 至少一个导电金属垫设置在第一表面上。 每个金属柱形成在相应的导电金属垫上。 每个金属柱具有与第一凹入侧壁相对的凹侧壁和凸侧壁，并且凹侧壁和凸侧壁与相应的导电金属垫正交。

公开(公告)号：US20210327731A1

公开(公告)日：2021-10-21

申请号：US16849904

申请日：2020-04-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Wen CHANG ,  Yu-Ho HSU ,  Tai-Yuan HUANG ,  Ping-Feng YANG ,  Fu-Ting CHANG ,  Chin-Feng WANG

IPC: H01L21/67 ,  H01L21/687 ,  H01L25/065

Abstract: A mass transfer method, a mass transfer device and a buffer carrier are provided. The mass transfer method includes: (a) providing a plurality of electronic components disposed on a source carrier; (b) providing a buffer carrier including a plurality of adjusting cavities; and (c) transferring the electronic components from the source carrier to the buffer carrier, wherein the electronic components are placed in the adjusting cavities of the buffer carrier to adjust positions of the electronic components from shifted positions to correct positions.

公开(公告)号：US20170278814A1

公开(公告)日：2017-09-28

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Dao-Long CHEN ,  Ying-Ta CHIU ,  Ping-Feng YANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US20160358875A1

公开(公告)日：2016-12-08

申请号：US15239745

申请日：2016-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang HSIAO ,  Chiu-Wen LEE ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/00 ,  H01L25/00 ,  C22C9/02 ,  B23K35/26 ,  B23K1/00 ,  C22C13/00 ,  H01L25/065 ,  B23K35/30

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

Abstract translation: 半导体器件包括第一电路层，邻近第一电路层设置的铜柱，第二电路层和焊料层。 第二电路层包括电接触和设置在电接触上的表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁剂层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的两种或更多种的组合，第二IMC包括金和锡的组合，钯的组合 和锡，或两者。

公开(公告)号：US20200273724A1

公开(公告)日：2020-08-27

申请号：US16285002

申请日：2019-02-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Huang Han CHEN ,  Ping-Feng YANG

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/78

Abstract: A method for manufacturing a semiconductor package structure includes providing a semiconductor chip, encapsulating the semiconductor chip via a package body, the package body having a first surface opposite to a second surface, and coating a first self-assembled monolayer (SAM) over the first surface and the second surface of the package body.

公开(公告)号：US20160260677A1

公开(公告)日：2016-09-08

申请号：US14639535

申请日：2015-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang HSIAO ,  Chiu-Wen LEE ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.

Abstract translation: 本公开涉及一种半导体器件及其制造方法。 半导体器件包括半导体管芯，半导体元件和焊料层。 半导体管芯包括铜柱。 半导体元件包括表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁度层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的至少两种的组合。 第二个IMC是金和锡的组合，钯和锡的组合，或两者兼而有之。

公开(公告)号：US20190214323A1

公开(公告)日：2019-07-11

申请号：US16354049

申请日：2019-03-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH ,  Hong-Ping LIN ,  Dao-Long CHEN ,  Ping-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/29 ,  C08G59/42 ,  C08K5/5435 ,  C08K5/544 ,  C08K3/04 ,  C08K3/36 ,  H01L23/00 ,  C09D163/00

CPC classification number: H01L23/295 ,  C08G59/42 ,  C08K3/04 ,  C08K3/36 ,  C08K5/5435 ,  C08K5/544 ,  C09D163/00 ,  H01L21/563 ,  H01L23/296 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a filler composition, wherein the filler composition includes particles each including both carbon and silica, wherein the filler composition is substantially devoid of alumina or silicon carbide, and the filler composition has a weight ratio of carbon to silica of at least greater than 1.0.

公开(公告)号：US20190148326A1

公开(公告)日：2019-05-16

申请号：US16247437

申请日：2019-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Dao-Long CHEN ,  Ying-Ta CHIU ,  Ping-Feng YANG

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US20180226320A1

公开(公告)日：2018-08-09

申请号：US15429024

申请日：2017-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Jia-Rung HO ,  Jin-Feng YANG ,  Chih-Pin HUNG ,  Ping-Feng YANG

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/373 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83493 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15321 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/29099

Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.

公开(公告)号：US20180114762A1

公开(公告)日：2018-04-26

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta CHIU ,  Chiu-Wen LEE ,  Dao-Long CHEN ,  Po-Hsien SUNG ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/06 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/565 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.