公开(公告)号：US20240213362A1

公开(公告)日：2024-06-27

申请号：US18069802

申请日：2022-12-21

Applicant: Analog Devices, Inc.

Inventor： Daniel Piedra ,  James G. Fiorenza

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Techniques to fabricate an enhancement mode HEMT device where the normally off characteristic is implemented through the backside of the device by epitaxially growing a semiconductor layer, such as aluminum nitride (AlN) or aluminum gallium nitride (AlGaN), to deplete a two-dimensional electron gas (2DEG) channel. This buried semiconductor layer, e.g., a buried AlN or AlGaN layer, advantageously maintains a high transconductance and is more amenable to gate scaling then other enhancement mode techniques.

公开(公告)号：US20230299156A1

公开(公告)日：2023-09-21

申请号：US18245451

申请日：2021-09-14

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza et al. ,  Daniel Piedra

IPC: H01L29/417 ,  H01L29/20 ,  H01L29/423 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01L29/778 ,  H01L29/66 ,  H01L23/367

CPC classification number: H01L29/41725 ,  H01L23/3672 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/66 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66462 ,  H01L29/7786

Abstract: In one or more implementations, a semiconductor device can include a first compound semiconductor device coupled to a second compound semiconductor device coupled in a face-to-face arrangement. The first compound semiconductor device can be coupled to the second compound semiconductor device such that a cavity is formed that includes a first gate electrical contact of the first compound semiconductor device and a second gate electrical contact of the second compound semiconductor device. A gap can be present between the first gate electrical contact and the second gate electrical contact.

公开(公告)号：US20230141865A1

公开(公告)日：2023-05-11

申请号：US18049543

申请日：2022-10-25

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Daniel Piedra ,  Leonard Shtargot ,  F. Jacob Steigerwald

IPC: H01L21/02 ,  H01L21/683

CPC classification number: H01L21/0254 ,  H01L21/683 ,  H01L21/0262

Abstract: A lateral GaN superjunction transistor or switching device that is configured to have higher breakdown voltage and lower on-resistance as compared to other GaN-based switching devices. The lateral GaN superjunction transistor includes a heavily doped buried implant region (hereinafter, “buried implant region”) in the substrate underlying the transistor that operates as backside field plate (BFP) to control or reduce gate-drain electric fields at the surface of the transistor, thereby enabling the transistor to operate at higher voltages while reducing charge trapping and breakdown effects. The lateral GaN superjunction transistor operates similarly to a vertical silicon superjunction FET to enable operation of the transistor at higher voltages than other GaN or semiconductor devices, such as to enable the construction of faster or higher power electronic circuits.

公开(公告)号：US11355598B2

公开(公告)日：2022-06-07

申请号：US16502285

申请日：2019-07-03

Applicant: Analog Devices, Inc.

Inventor： Puneet Srivastava ,  James G. Fiorenza ,  Daniel Piedra

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/20

Abstract: A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.

公开(公告)号：US20250098195A1

公开(公告)日：2025-03-20

申请号：US18291799

申请日：2021-08-03

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Daniel Piedra

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/778

Abstract: Various techniques for impurity dopant reduction in GaN regrowth are described. In a first technique, a barrier layer, such as AlN, can be formed at a regrowth interface before the regrown GaN layer. The barrier layer can bury the impurities at the regrowth interface and reduce their effect on the layers above that include the channel of the device, e.g., transistor. In a second technique, a buffer layer, such as a carbon-doped GaN layer, can be formed at the regrowth interface before the regrown GaN layer. Carbon can act as an acceptor to compensate for the dopants. e.g., silicon, and cancel their electronic effect on the above layers. In a third technique, a hydrogen bake treatment can be performed before the GaN regrowth. Hydrogen can desorb a thin layer of GaN at the regrowth interface, which is the GaN layer with the highest concentration of impurities.

公开(公告)号：US20240332397A1

公开(公告)日：2024-10-03

申请号：US18576324

申请日：2022-01-06

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Daniel Piedra

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/7786

Abstract: A gallium nitride (GaN) semiconductor device, such as a field-effect transistor (FET), is described with a design that can enable the semiconductor device to handle high current and high voltage simultaneously. For example, the device can have highly doped n-type N+ regions to ensure low contact resistance and high current. The semiconductor device can have a lightly conducting region next to the drain side of the gate contact, and the device can have a more highly conducting region further from the edge of the drain side of the gate contact. The semiconductor device can handle high current because of the low contact resistance and highly doped drain region but can handle a high electric field because of the lightly doped region near the drain edge of the gate contact. The semiconductor device can be formed in GaN by forming the original N+/N− structure, and then etching a portion of it away, and then regrowing the barrier layer.

公开(公告)号：US12087713B2

公开(公告)日：2024-09-10

申请号：US18148982

申请日：2022-12-30

Applicant: Analog Devices, Inc.

Inventor： Daniel Piedra ,  James G. Fiorenza ,  Puneet Srivastava ,  Andrew Proudman ,  Kenneth Flanders ,  Denis Michael Murphy ,  Leslie P. Green ,  Peter R. Stubler

IPC: H01L23/66 ,  H01L21/285 ,  H01L21/8252 ,  H01L23/48 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02 ,  H01L23/532 ,  H01L29/417

CPC classification number: H01L23/66 ,  H01L21/28575 ,  H01L21/8252 ,  H01L23/481 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L23/53214 ,  H01L29/4175 ,  H01L2223/6616 ,  H01L2223/6683 ,  H01L2924/1423

Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

公开(公告)号：US11637096B2

公开(公告)日：2023-04-25

申请号：US17837671

申请日：2022-06-10

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Puneet Srivastava ,  Daniel Piedra

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

公开(公告)号：US20220310578A1

公开(公告)日：2022-09-29

申请号：US17837671

申请日：2022-06-10

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Puneet Srivastava ,  Daniel Piedra

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

公开(公告)号：US20220093779A1

公开(公告)日：2022-03-24

申请号：US17275527

申请日：2019-09-11

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Puneet Srivastava ,  Daniel Piedra

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L21/266 ,  H01L29/205 ,  H01L29/20

Abstract: An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.