公开(公告)号：US09236029B2

公开(公告)日：2016-01-12

申请号：US14023412

申请日：2013-09-10

Applicant: APPLE INC.

Inventor： Ulrich T. Barnhoefer ,  Robert E. Jeter

IPC: G09G5/10 ,  G09G3/34 ,  G09G3/36 ,  G06T5/40 ,  H04N1/60 ,  H04N5/57 ,  H04N1/40

CPC classification number: G09G5/10 ,  G09G3/3406 ,  G09G3/3607 ,  G09G2320/0271 ,  G09G2320/0626 ,  G09G2320/0646 ,  G09G2360/16

Abstract: Systems, methods, and devices are provided for histogram generation and evaluation used in adjusting the power consumed by a backlight of an electronic display. One such method involves generating a pixel brightness histogram of an image frame passing through a pixel pipeline in a nonlinear space. One or more pixel brightness values from the histogram may be selected before being converted from the nonlinear space into a linear space. A tone mapping function and backlight intensity are determined based at least in part on the one or more pixel brightness values in the linear space. The resulting tone mapping function is converted to the nonlinear space and applied to the image frame or a subsequent image frame in the pixel pipeline. The pixels of the image frame to which the nondistorting portion of the tone mapping function is applied may appear substantially undistorted despite a reduction in backlight intensity.

Abstract translation: 提供了系统，方法和设备用于调整电子显示器的背光消耗的功率的直方图生成和评估。 一种这样的方法涉及生成通过非线性空间中的像素流水线的图像帧的像素亮度直方图。 在从非线性空间转换成线性空间之前，可以选择来自直方图的一个或多个像素亮度值。 至少部分地基于线性空间中的一个或多个像素亮度值来确定色调映射功能和背光强度。 所得到的色调映射函数被转换为非线性空间，并应用于像素管线中的图像帧或后续图像帧。 即使应用了色调映射功能的非失真部分的图像帧的像素也可能基本上不失真，尽管背光强度降低。

公开(公告)号：US20220270664A1

公开(公告)日：2022-08-25

申请号：US17181979

申请日：2021-02-22

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/06

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

公开(公告)号：US11217285B1

公开(公告)日：2022-01-04

申请号：US16986116

申请日：2020-08-05

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G11C7/10 ,  G06F11/10

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US20210183414A1

公开(公告)日：2021-06-17

申请号：US16716616

申请日：2019-12-17

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US09891853B1

公开(公告)日：2018-02-13

申请号：US15000626

申请日：2016-01-19

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Gurjeet S. Saund ,  Rakesh L. Notani ,  Robert E. Jeter

IPC: G06F3/06 ,  G11C7/22 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1689 ,  G11C7/222 ,  G11C2207/2254

Abstract: A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

公开(公告)号：US09691470B1

公开(公告)日：2017-06-27

申请号：US15188928

申请日：2016-06-21

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani

IPC: G11C7/06 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: An apparatus and method for a restricted range calibration is disclosed. A system includes a memory coupled to a memory controller. The memory controller is coupled to receive a clock signal, and is configured to operate in different performance states corresponding to different frequencies of the clock signal. The memory controller provides a data strobe signal to synchronize transfers of data to and from the memory. When operating in a first performance state, the memory controller may perform a first calibration of a delay applied to the data strobe signal. Performing the first calibration includes varying the delay over a first range of values. Thereafter, responsive to returning to the first performance state from another performance state, the memory controller may perform a second calibration. The second calibration includes varying the delay over a second range of values that is less than the first range.

公开(公告)号：US09672882B1

公开(公告)日：2017-06-06

申请号：US15083909

申请日：2016-03-29

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani

IPC: G11C7/22 ,  G11C29/04

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C2207/2254

Abstract: A method and apparatus for memory subsystem calibration in which periodic calibrations of a data strobe delay and reference voltage are scheduled. After a first calibration, a reference score is determined based on a parameter of an eye opening. On a next scheduled calibration thereafter, the data strobe delay is calibrated at the most recent value of the reference voltage. A score is then determined, and compared to the reference score. If the score is within a specified range of the reference score, then no calibration of the reference voltage is performed on the current cycle. Otherwise, the reference voltage is calibrated as well.

公开(公告)号：US20160364345A1

公开(公告)日：2016-12-15

申请号：US14738265

申请日：2015-06-12

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Neeraj Parik

IPC: G06F13/16 ,  G11C8/18 ,  G11C7/10 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F13/161 ,  G06F12/023 ,  G06F12/0646 ,  G06F2212/1044 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller. Additionally, in some embodiments, storing the configuration information may result in the configuration information being transmitted to the memory interface circuit more efficiently.

Abstract translation: 在一些实施例中，存储器接口系统包括存储器接口电路和存储器控制器。 存储器接口电路被配置为与存储器件通信。 存储器控制器被配置为响应于以第一频率工作的存储器件来存储与在第二频率下操作的存储器件对应的配置信息。 存储器控制器还被配置为响应于存储器件转换到第二频率，将配置信息发送到存储器接口电路。 在一些实施例中，存储配置信息可能导致与其中配置信息未被存储在存储器控制器的不同的存储器接口系统相比更快地提供给存储器设备的一些存储器请求。 此外，在一些实施例中，存储配置信息可以导致更有效地将配置信息发送到存储器接口电路。

公开(公告)号：US09396778B1

公开(公告)日：2016-07-19

申请号：US14820815

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1009 ,  G06F13/1689 ,  G11C7/00 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method and apparatus for conditional cancellation of a calibration procedure is performed. In one embodiment, a memory controller is coupled to memory. The memory controller is configured to convey data and a data strobe signal to the memory. The memory controller may conduct calibrations of a delay of the data strobe signal to ensure sufficient setup and hold time for the data. After an initial calibration, and at each of a number of periodic intervals, the memory controller may determine whether one or more parameters is within a specified range. If one of the one or more parameters is not within its respective specified range, another calibration of the data strobe delay may be performed. However, if each of the one or more parameters is within its respective specified range, the calibration may be canceled.

Abstract translation: 执行用于校准过程的条件消除的方法和装置。 在一个实施例中，存储器控制器耦合到存储器。 存储器控制器被配置为将数据和数据选通信号传送到存储器。 存储器控制器可以进行数据选通信号的延迟的校准，以确保数据的足够的建立和保持时间。 在初始校准之后，并且在多个周期性间隔的每一个周期，存储器控制器可以确定一个或多个参数是否在指定范围内。 如果一个或多个参数中的一个不在其相应的指定范围内，则可执行数据选通延迟的另一校准。 然而，如果一个或多个参数中的每一个在其各自的指定范围内，则可以取消校准。

公开(公告)号：US20160034219A1

公开(公告)日：2016-02-04

申请号：US14450525

申请日：2014-08-04

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Neeraj Parik ,  Kai Lun Hsiung

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0683 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1689

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit.The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. The memory interface unit may be configured to operate in a normal mode and a low power mode. However, in response to an occurrence of a given predetermined interval while the memory interface unit is in the low power mode, the memory interface unit may be configured to calibrate the timing unit subsequent to transitioning to the normal mode.

Abstract translation: 系统包括具有一个或多个存储阵列的存储器单元，以及可以耦合在存储器控制器和存储器单元之间的存储器接口单元。 存储器接口单元可以包括可以生成用于控制对存储器单元的读取和写入访问的定时信号的定时单元，以及可以以预定间隔校准定时单元的控制单元。 存储器接口单元可以被配置为在正常模式和低功率模式下操作。 然而，响应于在存储器接口单元处于低功率模式时发生给定的预定间隔，存储器接口单元可以被配置为在转换到正常模式之后校准定时单元。