公开(公告)号：US20240145246A1

公开(公告)日：2024-05-02

申请号：US17973927

申请日：2022-10-26

Applicant: Applied Materials, Inc.

Inventor： Yi Yang ,  In Soo Jung ,  Sean S. Kang ,  Srinivas D. Nemani ,  Papo Chen ,  Ellie Y. Yieh

IPC: H01L21/223 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/223 ,  H01L21/02236 ,  H01L21/3065

Abstract: Embodiments of the present technology include semiconductor processing methods. The methods may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The methods may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The methods may include forming a doped silicon-containing material on the silicon-containing material. The methods may include oxidizing the substrate. The oxidizing may form an oxidized doped silicon-containing material. The methods may include etching the oxidized doped silicon-containing material.

公开(公告)号：US11880137B2

公开(公告)日：2024-01-23

申请号：US18188676

申请日：2023-03-23

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Steven Hiloong Welch ,  Christopher S. Ngai

IPC: G03F7/09 ,  G03F7/20 ,  G03F7/16 ,  G03F7/11 ,  G03F7/004 ,  G03F7/039 ,  G03F7/40

CPC classification number: G03F7/094 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/11 ,  G03F7/168 ,  G03F7/203 ,  G03F7/2022 ,  G03F7/164 ,  G03F7/40

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US20230377875A1

公开(公告)日：2023-11-23

申请号：US18229285

申请日：2023-08-02

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. Citla ,  Soham Asrani ,  Joshua Rubnitz ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/02 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/311

CPC classification number: H01L21/02274 ,  H01L21/3065 ,  H01J37/32146 ,  H01L21/31116 ,  H01J2237/332 ,  H01J2237/334

Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

公开(公告)号：US11756828B2

公开(公告)日：2023-09-12

申请号：US16197048

申请日：2018-11-20

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun Wong ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76834 ,  H01L21/28562 ,  H01L21/76832 ,  H01L23/5329

Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.

公开(公告)号：US11650506B2

公开(公告)日：2023-05-16

申请号：US16600101

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Bangar ,  Christopher S. Ngai ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Steven Hiloong Welch

IPC: G03F7/11 ,  G03F7/20 ,  G03F7/09 ,  G03F7/16 ,  G03F7/40

CPC classification number: G03F7/2022 ,  G03F7/094 ,  G03F7/11 ,  G03F7/168 ,  G03F7/203 ,  G03F7/164 ,  G03F7/40

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US20230102558A1

公开(公告)日：2023-03-30

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US11566325B2

公开(公告)日：2023-01-31

申请号：US17120494

申请日：2020-12-14

Applicant: Applied Materials, Inc.

Inventor： Mei-Yee Shek ,  Bhargav S. Citla ,  Joshua Rubnitz ,  Jethro Tannos ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: C23C16/36 ,  C01B21/082 ,  C23C16/44 ,  C23C16/50 ,  C09D1/00

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

公开(公告)号：US11114306B2

公开(公告)日：2021-09-07

申请号：US16132837

申请日：2018-09-17

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Jethro Tannos ,  Jingyi Li ,  Douglas A. Buchberger, Jr. ,  Zhong Qiang Hua ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: C23C16/505 ,  H01L21/311 ,  H01L21/762 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/67 ,  C23C16/515 ,  H01L21/02 ,  C23C16/509 ,  C23C16/517

Abstract: Embodiments of the present invention provide an apparatus and methods for depositing a dielectric material using RF bias pulses along with remote plasma source deposition for manufacturing semiconductor devices, particularly for filling openings with high aspect ratios in semiconductor applications. In one embodiment, a method of depositing a dielectric material includes providing a gas mixture into a processing chamber having a substrate disposed therein, forming a remote plasma in a remote plasma source and delivering the remote plasma to an interior processing region defined in the processing chamber, applying a RF bias power to the processing chamber in pulsed mode, and forming a dielectric material in an opening defined in a material layer disposed on the substrate in the presence of the gas mixture and the remote plasma.

公开(公告)号：US20200161176A1

公开(公告)日：2020-05-21

申请号：US16197048

申请日：2018-11-20

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun WONG ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.

公开(公告)号：US10429747B2

公开(公告)日：2019-10-01

申请号：US15811341

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Mangesh Bangar ,  Srinivas D. Nemani ,  Steve G. Ghanayem ,  Ellie Y. Yieh

IPC: G03F7/20

Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.