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    APPARATUS AND METHOD
    11.
    发明申请
    APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20200293457A1

    公开(公告)日：2020-09-17

    申请号：US16778040

    申请日：2020-01-31

    Applicant: Arm Limited

    Inventor： Ilias VOUGIOUKAS ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Stephan DIESTELHORST

    IPC: G06F12/1027 ,  G06N5/04

    Abstract: Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.

    MEMORY ADDRESS TRANSLATION
    13.
    发明申请
    MEMORY ADDRESS TRANSLATION 审中-公开

    公开(公告)号：US20190243778A1

    公开(公告)日：2019-08-08

    申请号：US16342644

    申请日：2017-11-29

    Applicant: ARM LIMITED

    Inventor： Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Prakash S. RAMRAKHYANI ,  Stephan DIESTELHORST

    IPC: G06F12/1009 ,  G11C11/408 ,  G11C11/4096

    CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/657 ,  G11C8/06 ,  G11C11/4082 ,  G11C11/4096

    Abstract: Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the initial address space, one or more instances of the translation data; the translation data buffer comprising: an array of storage locations arranged in rows and columns; a row buffer comprising a plurality of entries each to store information from a respective portion of a row of the array; and comparison circuitry responsive to a key value dependent upon at least the initial memory address, to compare the key value with information stored in each of at least one key entry of the row buffer, each key entry having an associated value entry for storing at least a representation of a corresponding output memory address, and to identify which of the at least one key entry, if any, is a matching key entry storing information matching the key value; and output circuitry to output, when there is a matching key entry, at least the representation of the output memory address in the value entry associated with the matching key entry.

    CACHE SECTOR USAGE PREDICTION
    14.
    发明申请
    CACHE SECTOR USAGE PREDICTION 审中-公开

    公开(公告)号：US20180232313A1

    公开(公告)日：2018-08-16

    申请号：US15882104

    申请日：2018-01-29

    Applicant: ARM Limited

    Inventor： Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Jonas SVEDAS ,  Stephan DIESTELHORST

    IPC: G06F12/0871 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0808 ,  G06F12/0811 ,  G06F3/06

    CPC classification number: G06F12/0871 ,  G06F3/064 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0895 ,  G06F2212/6026

    Abstract: A system cache and method of operating a system cache are provided. The system cache provides data caching in response to data access requests from plural system components. The system cache has data caching storage with plural entries, each entry storing a block of data items and each block of data items comprising plural sectors of data items, and each block of data items being stored in an entry of the data caching storage with an associated address portion. Sector use prediction circuitry is provided which has a set of pattern entries to store a set of sector use patterns. In response to a data access request received from a system component specifying one or more data items a selected pattern entry is selected in dependence on a system component identifier in the data access request and a sector use prediction is generated in dependence on a sector use pattern in the selected pattern entry. Further data items may then be retrieved which are not specified in the data access request but are indicated by the sector use prediction, and memory bandwidth usage is thereby improved.

    SYSTEM AND METHOD FOR CONTROLLING THE POWER MODE OF OPERATION OF A MEMORY DEVICE
    15.
    发明申请
    SYSTEM AND METHOD FOR CONTROLLING THE POWER MODE OF OPERATION OF A MEMORY DEVICE 审中-公开
    用于控制存储器件的操作的功率模式的系统和方法

    公开(公告)号：US20160154452A1

    公开(公告)日：2016-06-02

    申请号：US14557895

    申请日：2014-12-02

    Applicant: ARM LIMITED

    Inventor： Andreas HANSSON ,  Ashley John CRAWFORD ,  Michael Andrew CAMPBELL ,  Stephan DIESTELHORST

    IPC: G06F1/32 ,  G06F13/24 ,  G06F9/44

    CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A system and method are provided for controlling the power mode of operation of a memory device. The system includes a processing device for performing processing operations on data, and a memory controller associated with the memory device, the memory device being used to store data for access by the processing device. The memory controller has power mode control circuitry to switch the memory device between different power modes of operation. Further, an interrupt controller is configured to issue an event signal to the processing device to trigger performance of at least one processing operation. On issuing the event signal, the interrupt controller further initiates generation of a wakeup stimulus signal to the power mode control circuitry, and the power mode control circuitry is then arranged to determine whether to change the power mode of operation of the memory device in dependence on the wakeup stimulus signal. By such an approach, the wakeup stimulus signal can provide an early trigger to the power mode control circuitry to exit the memory device from at least one low power mode of operation in anticipation of the performance of the at least one processing operation by the processing device requiring data to be accessed in the memory device.

    Abstract translation: 提供了一种用于控制存储器件的功率工作模式的系统和方法。 该系统包括用于对数据执行处理操作的处理装置，以及与存储装置相关联的存储器控​​制器，该存储装置用于存储数据以供处理装置访问。 存储器控制器具有电源模式控制电路，以在不同的功率工作模式之间切换存储​​器件。 此外，中断控制器被配置为向处理设备发出事件信号以触发至少一个处理操作的执行。 在发出事件信号时，中断控制器进一步向功率模式控制电路启动唤醒激励信号的产生，然后将功率模式控制电路设置为根据以下方式确定是否改变存储器件的功率工作模式 唤醒刺激信号。 通过这种方法，唤醒激励信号可以提供早期的触发，使得功率模式控制电路从预期的至少一个低功率操作模式退出存储器件，以期预期处理设备执行至少一个处理操作 要求在存储设备中访问数据。

    CHECKING LOCK VARIABLES FOR TRANSACTIONS IN A SYSTEM WITH TRANSACTIONAL MEMORY SUPPORT
    16.
    发明申请
    CHECKING LOCK VARIABLES FOR TRANSACTIONS IN A SYSTEM WITH TRANSACTIONAL MEMORY SUPPORT 审中-公开

    公开(公告)号：US20200272505A1

    公开(公告)日：2020-08-27

    申请号：US16651178

    申请日：2018-08-30

    Applicant: ARM Limited

    Inventor： Matthew James HORSNELL ,  Stephan DIESTELHORST

    IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52

    Abstract: In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.

    INSTRUCTION SAMPLING WITHIN TRANSACTIONS
    18.
    发明申请
    INSTRUCTION SAMPLING WITHIN TRANSACTIONS 审中-公开

    公开(公告)号：US20170337115A1

    公开(公告)日：2017-11-23

    申请号：US15532286

    申请日：2015-11-23

    Applicant: ARM LIMITED

    Inventor： Michael John WILLIAMS ,  John Michael HORLEY ,  Stephan DIESTELHORST

    IPC: G06F11/36 ,  G06F9/46

    CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/455 ,  G06F9/46 ,  G06F9/467 ,  G06F11/362 ,  G06F11/3636 ,  G06F12/08 ,  G06F12/126

    Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.

    MONITORING UTILIZATION OF TRANSACTIONAL PROCESSING RESOURCE
    19.
    发明申请
    MONITORING UTILIZATION OF TRANSACTIONAL PROCESSING RESOURCE 审中-公开

    公开(公告)号：US20170329627A1

    公开(公告)日：2017-11-16

    申请号：US15537015

    申请日：2015-11-24

    Applicant: ARM LIMITED

    Inventor： Stephan DIESTELHORST ,  Matthew James HORSNELL

    IPC: G06F9/46 ,  G06F11/36 ,  G06F9/38

    CPC classification number: G06F9/467 ,  G06F9/3842 ,  G06F11/362

    Abstract: An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.

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