公开(公告)号：US07838862B2

公开(公告)日：2010-11-23

申请号：US11177115

申请日：2005-07-08

申请人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144

摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

摘要翻译： 一种包括多个存取晶体管的相位随机存取存储器，每个存取晶体管包括漏区和由多个存取晶体管共享的相变膜。 相变膜通过第一电极连接到位线，并通过多个第二电极中的至少一个连接到每个相应的漏极区域。

公开(公告)号：US20070133271A1

公开(公告)日：2007-06-14

申请号：US11605212

申请日：2006-11-29

申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

公开(公告)号：US20050247922A1

公开(公告)日：2005-11-10

申请号：US11177115

申请日：2005-07-08

申请人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C13/00 ,  G11B7/24 ,  G11C11/56 ,  G11C16/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L29/76 ,  H01L45/00 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144

摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

摘要翻译： 一种包括多个存取晶体管的相位随机存取存储器，每个存取晶体管包括漏极区域，以及由多个存取晶体管共享的可相位改变的薄膜。 相变膜通过第一电极连接到位线，并通过多个第二电极中的至少一个连接到每个相应的漏极区域。

公开(公告)号：US07668007B2

公开(公告)日：2010-02-23

申请号：US12124523

申请日：2008-05-21

申请人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

摘要翻译： 存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控​​制器。 电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电 位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平 高电压。

公开(公告)号：US20080232161A1

公开(公告)日：2008-09-25

申请号：US12124523

申请日：2008-05-21

申请人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

摘要翻译： 存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控​​制器。 电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电 位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平 高电压。

公开(公告)号：US07405960B2

公开(公告)日：2008-07-29

申请号：US11695232

申请日：2007-04-02

申请人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

发明人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

摘要： A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

摘要翻译： 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

公开(公告)号：US20080112208A1

公开(公告)日：2008-05-15

申请号：US11695232

申请日：2007-04-02

申请人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

发明人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

IPC分类号： G11C11/34 ,  G11C11/00 ,  G11C5/06

CPC分类号： G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

摘要： A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

摘要翻译： 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

公开(公告)号：US06943395B2

公开(公告)日：2005-09-13

申请号：US10805696

申请日：2004-03-22

申请人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C13/00 ,  G11B7/24 ,  G11C11/56 ,  G11C16/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L29/76 ,  H01L45/00 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144

摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

公开(公告)号：US07869271B2

公开(公告)日：2011-01-11

申请号：US12787571

申请日：2010-05-26

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US07994493B2

公开(公告)日：2011-08-09

申请号：US12196137

申请日：2008-08-21

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L29/04 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

摘要翻译： 相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。 字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。 第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。 多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。