公开(公告)号：US20080144356A1

公开(公告)日：2008-06-19

申请号：US11945420

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

摘要翻译： 提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝 所选择的电阻性存储单元的可变电阻材料。

公开(公告)号：US07920405B2

公开(公告)日：2011-04-05

申请号：US11957756

申请日：2007-12-17

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/0064 ,  B82Y10/00 ,  G11C11/15 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括具有字线，位线和非易失性存储器单元的存储单元阵列，每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取元件 线和相应的位线。 可变电阻材料具有根据要存储的数据而变化的电阻电平。 选择电路选择要写入数据的至少一个非易失性存储单元。 自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置，以将数据写入所选择的非易失性存储单元中并且改变（例如，增加） 写入偏置，直到所选择的非易失性存储单元的电阻水平变化。

公开(公告)号：US07869256B2

公开(公告)日：2011-01-11

申请号：US11957812

申请日：2007-12-17

申请人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： G11C13/00 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/009

摘要： A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.

摘要翻译： 使用非易失性存储器件，其中数据值由单元两端的极性确定。非易失性存储器件包括将行地址的多个预定位值解码为第一地址的第一解码器 并且设置在存储单元阵列的行方向上; 第二解码器，其将所述行地址的其他位值解码为第二地址，并且被布置在所述存储单元阵列的列方向上; 以及根据数据值对与第一地址或第二地址对应的字线施加偏置电压的驱动器。 通过包括第一和第二解码器并以两个步骤对行地址进行解码，根据本发明的双向RRAM可以在降低芯片尺寸的同时以高速执行寻址。

公开(公告)号：US07586776B2

公开(公告)日：2009-09-08

申请号：US11945420

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

摘要翻译： 提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝 所选择的电阻性存储单元的可变电阻材料。

公开(公告)号：US09042152B2

公开(公告)日：2015-05-26

申请号：US13562871

申请日：2012-07-31

申请人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C11/56

CPC分类号： G11C13/0033 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054

摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

摘要翻译： 包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。 感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号 第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

公开(公告)号：US20130311717A1

公开(公告)日：2013-11-21

申请号：US13768858

申请日：2013-02-15

申请人： Chan-kyung Kim ,  Dong-seok Kang ,  Hye-jin Kim ,  Chul-woo Park ,  Dong-hyun Sohn ,  Yun-sang Lee ,  Sang-beom Kang ,  Hyung-rok Oh ,  Soo-ho Cha

发明人： Chan-kyung Kim ,  Dong-seok Kang ,  Hye-jin Kim ,  Chul-woo Park ,  Dong-hyun Sohn ,  Yun-sang Lee ,  Sang-beom Kang ,  Hyung-rok Oh ,  Soo-ho Cha

IPC分类号： G11C11/16 ,  G06F12/02

CPC分类号： G11C11/165 ,  G06F12/0246 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

摘要翻译： 公开了一种磁性随机存取存储器（MRAM）及其存储器模块，包括该存储器模块的存储器系统及其控制方法。 MRAM包括被配置为根据磁化方向在至少两个状态之间改变的磁存储单元和支持多个操作模式的模式寄存器。

公开(公告)号：US20110170332A1

公开(公告)日：2011-07-14

申请号：US13011188

申请日：2011-01-21

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho ,  Joon-min Park

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho ,  Joon-min Park

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C5/145 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79

摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

摘要翻译： 集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。 提供读/写控制电路。 读/写控制电路包括读/写合并电路和列选择电路。 被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。 该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

公开(公告)号：US07894236B2

公开(公告)日：2011-02-22

申请号：US11945443

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Sang-beom Kang ,  Joon-min Park

发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Sang-beom Kang ,  Joon-min Park

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C5/145 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79

摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

摘要翻译： 集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。 提供读/写控制电路。 读/写控制电路包括读/写合并电路和列选择电路。 被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。 该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

公开(公告)号：US07701747B2

公开(公告)日：2010-04-20

申请号：US11958432

申请日：2007-12-18

申请人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00

CPC分类号： G11C13/00 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009

摘要： A non-volatile memory device, in which data values are determined by polarities at cell terminals, includes a memory cell array. The memory cell array is divided into multiple sub cell arrays, each sub cell array including at least one input/output line and an X-decoder/driver. First input/output lines included in different sub cell arrays may be simultaneously activated and bias voltages may be applied to the activated first input/output lines in accordance with the data values. The non-volatile memory device may be a bi-directional resistive random access memory (RRAM).

摘要翻译： 其中数据值由单元终端的极性确定的非易失性存储器件包括存储单元阵列。 存储单元阵列被分成多个子单元阵列，每个子单元阵列包括至少一个输入/输出线和X解码器/驱动器。 可以同时激活包括在不同子单元阵列中的第一输入/输出线，并且可以根据数据值将偏置电压施加到激活的第一输入/输出线。 非易失性存储器件可以是双向电阻随机存取存储器（RRAM）。

公开(公告)号：US20080151652A1

公开(公告)日：2008-06-26

申请号：US11945443

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Sang-beom Kang ,  Joon-min Park

发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Sang-beom Kang ,  Joon-min Park

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C5/145 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79

摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

摘要翻译： 集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。 提供读/写控制电路。 读/写控制电路包括读/写合并电路和列选择电路。 被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。 该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。