公开(公告)号：US5605855A

公开(公告)日：1997-02-25

申请号：US395339

申请日：1995-02-28

申请人： Ko-Min Chang ,  Marius Orlowski ,  Craig Swift ,  Shih-Wei Sun ,  Shiang-Chyong Luo

发明人： Ko-Min Chang ,  Marius Orlowski ,  Craig Swift ,  Shih-Wei Sun ,  Shiang-Chyong Luo

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8234

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66553

摘要： A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).

摘要翻译： 用于制造渐变沟道MOS器件的工艺包括在半导体衬底（10）的表面上形成掩模层（16），并通过栅氧化层（12）从表面分离。 使用掩模层（16）作为掺杂掩模，在半导体衬底（10）的沟道区（20）中形成第一掺杂区（22）。 第二掺杂区域（24）形成在沟道区域（20）中并且从半导体衬底（10）的主表面（14）延伸到第一掺杂区域（22）。 栅极电极（34）形成在掩模层（16）的开口（18）内，并与沟道区域（20）对准。 在去除掩模层（16）时，源极和漏极区（36,38）形成在半导体衬底（10）中并与栅电极（34）对齐。

公开(公告)号：US5399507A

公开(公告)日：1995-03-21

申请号：US265860

申请日：1994-06-27

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/76 ,  H01L21/822 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L21/84 ,  Y10S148/013

摘要： A mixed thin-film and bulk semiconductor substrate (10, 30) for integrated circuit applications is made with two different processes. In the first process, a standard wafer (11) is masked around its periphery (14). The internal unmasked portion (16) is implanted with an insulating species to form a buried dielectric layer (18), thus forming a mixed thin-film and bulk semiconductor substrate. Alternatively, a thin-film wafer may be masked on an internal portion (36) and then etched to expose a portion (40) of the underlying bulk substrate (11') around the periphery of the wafer. An epitaxial layer (50) is then grown to build up the exposed bulk portion to form the mixed substrate. An isolation region (24, 52, 46, 54) is formed at a boundary between the thin-film portion and the bulk portion. Devices (27, 28, 28') having different voltage requirements may then be formed overlying appropriate portions of the mixed substrate.

摘要翻译： 用于集成电路应用的混合薄膜和体半导体衬底（10,30）由两种不同的工艺制成。 在第一工艺中，标准晶片（11）围绕其周边（14）被掩蔽。 内部未屏蔽部分（16）注入绝缘材料以形成掩埋介电层（18），从而形成混合的薄膜和体半导体衬底。 或者，薄膜晶片可以被掩蔽在内部部分（36）上，然后被蚀刻以暴露围绕晶片周边的下面的块状基板（11'）的部分（40）。 然后生长外延层（50）以构成暴露的本体部分以形成混合的衬底。 在薄膜部分和本体部分之间的边界处形成隔离区域（24,52,46,54）。 然后可以形成具有不同电压要求的装置（27,28,28'），覆盖混合基板的适当部分。

公开(公告)号：US08062536B2

公开(公告)日：2011-11-22

申请号：US12729234

申请日：2010-03-22

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/467 ,  H01L21/32 ,  H01L21/308 ,  H01L21/762

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。 第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。 防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。 可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

公开(公告)号：US20080242020A1

公开(公告)日：2008-10-02

申请号：US11692912

申请日：2007-03-28

申请人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Shih-Wei Sun

发明人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Shih-Wei Sun

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 首先制备位于半导体衬底上的半导体衬底和栅极结构。 源极区域和漏极区域包括在栅极结构的两个相对侧上的半导体衬底中。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构，源极区和漏极区。 接下来，进行惰性气体处理以改变应力帽层的应力值。 由于通过本发明可以容易地调整应力覆盖层的应力值，因此可以将一个应力覆盖层施加到N型MOS晶体管和P型MOS晶体管两者。

公开(公告)号：US07378740B2

公开(公告)日：2008-05-27

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US20060099824A1

公开(公告)日：2006-05-11

申请号：US11315904

申请日：2005-12-22

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  W.B. Shieh ,  J.Y. Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  W.B. Shieh ,  J.Y. Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/31

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

公开(公告)号：US06214671B1

公开(公告)日：2001-04-10

申请号：US09223151

申请日：1998-12-30

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L21336

CPC分类号： H01L21/823842 ,  H01L21/28052 ,  H01L29/4933 ,  H01L29/665

摘要： A method of forming a dual gate structure provides a substrate, in which a first well with a first conductive type and a second well with a second conductive type are formed. An isolation structure is formed between the first well and the second well. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. A part of the polysilicon layer positioned on the first well is doped to become a first type polysilicon layer. Another part of the polysilicon layer positioned on the second well is doped to become a second type polysilicon layer. An undoped polysilicon layer is formed on the doped polysilicon layer. A part of the undoped polysilicon and a part of the doped polysilicon layer are removed to form a first gate on the first well and a second gate on the second well. Spacers are formed on the sidewalls of the first gate and on the second gate. Source/drain regions are formed in the substrate beside the first gate and the second gate. Silicide is formed on the first gate, the second gate and the source/drain regions by self-alignment to form a dual gate structure comprising the first gate and the second gate.

摘要翻译： 形成双栅极结构的方法提供了一种衬底，其中形成具有第一导电类型的第一阱和具有第二导电类型的第二阱。 在第一井和第二井之间形成隔离结构。 在衬底上形成栅氧化层。 在栅氧化层上形成多晶硅层。 位于第一阱的多晶硅层的一部分被掺杂成为第一类型的多晶硅层。 位于第二阱上的多晶硅层的另一部分被掺杂以成为第二类型的多晶硅层。 在掺杂多晶硅层上形成未掺杂的多晶硅层。 去除未掺杂多晶硅的一部分和掺杂多晶硅层的一部分，以在第一阱上形成第一栅极，在第二阱上形成第二栅极。 间隔件形成在第一门的侧壁和第二门上。 源极/漏极区域形成在第一栅极和第二栅极旁边的衬底中。 通过自对准在第一栅极，第二栅极和源极/漏极区域上形成硅化物以形成包括第一栅极和第二栅极的双栅极结构。

公开(公告)号：US06200629B1

公开(公告)日：2001-03-13

申请号：US09228186

申请日：1999-01-12

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： B05D512

CPC分类号： H01L21/76897 ,  H01L27/0805 ,  H01L28/55

摘要： A method for manufacturing a capacitor includes the steps of forming a dielectric layer over a substrate, and then forming at least one contact within the dielectric layer. Next, a first metal layer is formed on the dielectric layer and an electromigration layer is formed on the first metal layer. A patterned capacitor dielectric layer is formed on the electromigration layer in a capacitor area. A second metal layer is then formed over the substrate and defined; a portion of second metal serving as an upper electrode of the capacitor is therefore formed on the electromigration layer. A portion of the second metal layer on the contact serves as a portion of the via of the interconnects. The electromigration layer is self-alignedly patterned when patterning the second metal layer, and a portion of the electromigration layer serves as a lower electrode of the capacitor. The electromigration layer on the contact in the via area is used to prevent electromigration.

摘要翻译： 制造电容器的方法包括以下步骤：在衬底上形成电介质层，然后在电介质层内形成至少一个接触。 接着，在电介质层上形成第一金属层，在第一金属层上形成电迁移层。 在电容器区域的电迁移层上形成图案化的电容器介电层。 然后在衬底上形成第二金属层并定义; 因此，在电迁移层上形成用作电容器的上电极的第二金属的一部分。 接触件上的第二金属层的一部分用作互连通孔的一部分。 当图案化第二金属层时，电迁移层是自对准图案，并且电迁移层的一部分用作电容器的下电极。 通孔区域上的触点上的电迁移层用于防止电迁移。

公开(公告)号：US6100205A

公开(公告)日：2000-08-08

申请号：US958828

申请日：1997-10-28

申请人： Chih-Chien Liu ,  J. Y. Wu ,  Tsang-Jung Lin ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  J. Y. Wu ,  Tsang-Jung Lin ,  Water Lur ,  Shih-Wei Sun

IPC分类号： C23C16/04 ,  C23C16/40 ,  C23C16/50 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31

CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/402 ,  C23C16/50 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76801

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.

摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积介电层。 执行第一HDPCVD步骤以在布线上形成布线之间的间隙中的第一介电层。 执行PECVD步骤以将电介质材料沉积在第一介电层上并且在间隙内并限定开口。 执行第二HDPCVD步骤，并且由PECVD步骤限定的开口被第三介电层覆盖。 该方法允许以相当可控的方式在相邻的金属布线之间形成空气填充的空隙，这允许选择空隙的形状和空隙的顶部的精确定位。 此外，空隙通过比典型的更致密和更耐用的材料密封。

公开(公告)号：US6020258A

公开(公告)日：2000-02-01

申请号：US982266

申请日：1997-12-01

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76834 ,  Y10S438/97

摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.

摘要翻译： 形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。 在层间电介质的表面上设置一级布线。 第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。 金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。 去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。