公开(公告)号：US20110090198A1

公开(公告)日：2011-04-21

申请号：US12582107

申请日：2009-10-20

申请人： Fu-Lung HSUEH ,  Yung-Chow PENG ,  Kuo-Liang DENG

发明人： Fu-Lung HSUEH ,  Yung-Chow PENG ,  Kuo-Liang DENG

IPC分类号： G09G5/00 ,  H03M1/66 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/02 ,  G09G2330/021

摘要： A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.

摘要翻译： 一种方法包括响应于接收数字控制信号的第一位数而输出来自第一DAC解码器电路的第一信号，响应于接收到数字控制信号的第二位数而从第二DAC解码器电路输出第二信号 并且从耦合到第一和第二DAC解码器电路的缓冲器交替地将第一和第二信号之一输出到LCD列。 第一信号具有等于在第一DAC解码器电路的第一多个输入端之一处接收的第一多个电压电平之一的电压电平。 第二信号具有等于在第二DAC解码器电路的第二多个输入端之一处接收的第二多个电压电平之一的电压电平。

公开(公告)号：US20110090012A1

公开(公告)日：2011-04-21

申请号：US12894903

申请日：2010-09-30

申请人： Chewn-Pu JOU ,  Fu-Lung HSUEH ,  Sally LIU

发明人： Chewn-Pu JOU ,  Fu-Lung HSUEH ,  Sally LIU

IPC分类号： H03F3/16

CPC分类号： H03F3/19 ,  H01L29/78

摘要： A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate.

摘要翻译： 射频放大器电路包括能够接收衬底偏置电压的衬底。 晶体管的源极能够接收源极偏置电压。 晶体管的漏极能够接收漏极偏置电压。 晶体管的栅极位于源极和漏极之间。 射频输入信号耦合到门。 衬底偏置电路提供衬底偏置电压。 衬底偏置电压和源极偏置电压正向偏置由源极和衬底形成的第一二极管。 衬底偏置电压和漏极偏置电压反向偏置由漏极和衬底形成的第二二极管。

公开(公告)号：US20120068745A1

公开(公告)日：2012-03-22

申请号：US12887984

申请日：2010-09-22

申请人： Hsieh-Hung HSIEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： Hsieh-Hung HSIEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H03L7/08 ,  H03B19/12

CPC分类号： H03L7/18

摘要： A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is electrically connected to the differential direct injection pair and produces an operating frequency based on the mixed differential injection signals.

摘要翻译： 代表性的注入锁定分频器包括被配置为接收和混合差分注入信号的差分直接注入对以及电连接到差分直接注入对的振荡器，并且基于混合的差分注入信号产生工作频率。

公开(公告)号：US20120056769A1

公开(公告)日：2012-03-08

申请号：US12874462

申请日：2010-09-02

申请人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H03M1/50

CPC分类号： G04F10/005

摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

摘要翻译： 公开了时间到数字转换（TDC）的方法和装置。 定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。 校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。 被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。

公开(公告)号：US20120032743A1

公开(公告)日：2012-02-09

申请号：US12968342

申请日：2010-12-15

申请人： Hsieh-Hung HSIEH ,  Po-Yi WU ,  Ho-Hsiang CHEN ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： Hsieh-Hung HSIEH ,  Po-Yi WU ,  Ho-Hsiang CHEN ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H03G3/30 ,  H03F3/16 ,  H03F1/22

CPC分类号： H03G1/0029 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/249 ,  H03F2200/318 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/492

摘要： A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.

摘要翻译： 低噪声放大器（“LNA”）包括第一共源共栅增益级，其包括被配置为接收射频（“RF”）输入信号的第一互补金属氧化物半导体（“CMOS”）晶体管和耦合到 输出节点。 第一感应栅极网络耦合到第二CMOS晶体管的栅极，用于增加第一共源共栅增益级的增益。 第一感应栅极网络具有非零电感输入阻抗并且包括至少一个无源电路元件。

公开(公告)号：US20110304372A1

公开(公告)日：2011-12-15

申请号：US12813620

申请日：2010-06-11

申请人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H03H11/26

CPC分类号： G04F10/005

摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

公开(公告)号：US20110219876A1

公开(公告)日：2011-09-15

申请号：US12720813

申请日：2010-03-10

申请人： Alexander KALNITSKY ,  Fu-Lung HSUEH

发明人： Alexander KALNITSKY ,  Fu-Lung HSUEH

IPC分类号： G01P15/125

CPC分类号： G01B7/003 ,  A63F13/06 ,  A63F13/211 ,  A63F13/24 ,  A63F2300/1043 ,  A63F2300/105 ,  G01P3/52 ,  G01P15/125 ,  G01P15/16

摘要： An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.

摘要翻译： 一种用于检测微机电系统中的机械位移的装置包括具有彼此间隔开的第一和第二板的电容器，所述第一和第二板具有不同的功函数并且彼此电连接。 电容器板可以相对于彼此移动，使得板之间的间隔响应于力而变化。 通过电容器的电流表示给定时间间板间距的变化率。

公开(公告)号：US20100244144A1

公开(公告)日：2010-09-30

申请号：US12731325

申请日：2010-03-25

申请人： Fu-Lung HSUEH ,  Tao Wen CHUNG ,  Po-Yao KE ,  Shine CHUNG

发明人： Fu-Lung HSUEH ,  Tao Wen CHUNG ,  Po-Yao KE ,  Shine CHUNG

IPC分类号： H01L23/62 ,  H01L27/06

CPC分类号： H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

摘要翻译： 在各种实施例中，熔丝由硅化物形成，并且在翅片结构的翅片的顶部上形成。 因为熔丝形成在翅片的顶部，所以它的宽度取得了非常薄的翅片的宽度。 根据实施方案，保险丝也使用平面技术形成并且包括薄的宽度。 因为保险丝的宽度较薄，所以能够可靠地使保险丝断开。 此外，熔丝可以与晶体管一起使用以形成用于存储器阵列的存储单元，并且晶体管利用FinFET技术。

公开(公告)号：US20130241634A1

公开(公告)日：2013-09-19

申请号：US13419911

申请日：2012-03-14

申请人： Hsieh-Hung HSIEH ,  Yi-Hsuan LIU ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： Hsieh-Hung HSIEH ,  Yi-Hsuan LIU ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H01L25/00

CPC分类号： H01L23/48 ,  H01L23/66 ,  H01L25/0657 ,  H01L2225/06531 ,  H01L2924/0002 ,  H04B5/0075 ,  H01L2924/00

摘要： An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.

摘要翻译： 集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。 第一芯片包括射频电路和电耦合到射频电路的第一线圈。 第二芯片包括校准电路和电耦合到校准电路的第二线圈。 校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

公开(公告)号：US20120122395A1

公开(公告)日：2012-05-17

申请号：US12946072

申请日：2010-11-15

申请人： Tzu-Jin YEH ,  Hsieh-Hung HSIEH ,  Jun-De JIN ,  Ming Hsien TSAI ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： Tzu-Jin YEH ,  Hsieh-Hung HSIEH ,  Jun-De JIN ,  Ming Hsien TSAI ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H04B5/00

CPC分类号： H04B5/0081

摘要： Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

摘要翻译： 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。