利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.023 秒)

    Methods of fabricating semiconductor devices with scalable two transistor memory cells
    12.
    发明申请
    Methods of fabricating semiconductor devices with scalable two transistor memory cells 失效
    用可扩展的双晶体管存储单元制造半导体器件的方法

    公开(公告)号：US20050156225A1

    公开(公告)日：2005-07-21

    申请号：US11040229

    申请日：2005-01-21

    申请人： Su-Jin Ahn ,  Gwan-Hyeob Koh ,  Hyoung-Joon Kim

    发明人： Su-Jin Ahn ,  Gwan-Hyeob Koh ,  Hyoung-Joon Kim

    IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/7881

    摘要： Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

    摘要翻译： 公开了具有可伸缩的双晶体管存储单元的半导体器件及其制造方法。 半导体器件包括其上具有第一，第二和第三隔离层的半导体衬底。 第一和第二隔离层间隔开以限定它们之间的第一有源区，并且第二隔离层和第三隔离层同样隔开以在它们之间形成第二有源区。 在每个有源区域上提供一个单元栅极，该栅极电介质层，存储节点，多个隧道结屏障和源层依次堆叠。 该装置还包括围绕电池栅极的每个侧壁的至少一部分的第一和第二控制线。 电介质层可以插在电池栅极的侧壁和围绕它的控制线之间。 数据线连接到单元门。

    Method of fabricating contact pads of a semiconductor device
    13.
    发明授权
    Method of fabricating contact pads of a semiconductor device 有权
    制造半导体器件的接触焊盘的方法

    公开(公告)号：US06458680B2

    公开(公告)日：2002-10-01

    申请号：US09371835

    申请日：1999-08-11

    申请人： Tae-Young Chung ,  Jae-Goo Lee ,  Gwan-Hyeob Koh

    发明人： Tae-Young Chung ,  Jae-Goo Lee ,  Gwan-Hyeob Koh

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/76895

    摘要： An upper insulating layer is formed on a semiconductor substrate, the upper insulating layer having an etch selection ratio relative to a lower insulating layer. The upper insulating layer is anisotropically etched by using a contact pad forming mask, to form an opening exposing an upper surface of the semiconductor substrate between conductive patterns on the substrate. The side walls of the upper insulating layer are then isotropically etched, using the above mask again, to expand the size of the opening. The expanded opening is then filled with a conductive layer to form a contact pad to be electrically connected to the semiconductor substrate.

    摘要翻译： 在半导体衬底上形成上绝缘层，上绝缘层相对于下绝缘层具有蚀刻选择比。 通过使用接触焊盘形成掩模对上绝缘层进行各向异性蚀刻，以形成在衬底上的导电图案之间暴露半导体衬底的上表面的开口。 然后再次使用上述掩模对上绝缘层的侧壁进行各向同性蚀刻，以扩大开口的尺寸。 然后用导电层填充扩大的开口以形成电连接到半导体衬底的接触焊盘。

    Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same
    14.
    发明申请
    Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same 审中-公开
    磁阻随机存取存储器件及其制造方法

    公开(公告)号：US20170054070A1

    公开(公告)日：2017-02-23

    申请号：US15146355

    申请日：2016-05-04

    申请人： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

    发明人： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

    IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

    CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    摘要： In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

    摘要翻译： 在制造MRAM器件的方法中，在衬底上形成包括下电极，MTJ结构和顺序层叠的上电极的存储单元。 在衬底上形成包括依次堆叠的覆盖层，牺牲层和蚀刻停止层的保护层结构以覆盖存储单元。 在保护层结构上形成绝缘中间层。 形成绝缘中间层以形成露出保护层结构的开口。 暴露的保护层结构被部分去除以暴露上电极。 在暴露的上电极上形成布线以填充开口。

    Non-volatile memory devices including stacked NAND-type resistive memory cell strings
    19.
    发明授权
    Non-volatile memory devices including stacked NAND-type resistive memory cell strings 有权
    非易失性存储器件包括堆叠的NAND型电阻存储器单元串

    公开(公告)号：US08036018B2

    公开(公告)日：2011-10-11

    申请号：US12917175

    申请日：2010-11-01

    申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

    发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C11/00 ,  G11C5/06

    CPC分类号： G11C13/003 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

    摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

    摘要翻译： 非易失性存储器件包括衬底，衬底上的绝缘层和堆叠在绝缘层中的多个串联连接的电阻性存储器单元，使得多个电阻存储器单元中的第一个位于衬底上，下一个 多个电阻存储器单元中的一个位于多个电阻存储器单元中的第一个上，以限定NAND型电阻存储单元串。 绝缘层上的位线电连接到多个电阻存储单元中的最后一个。 多个电阻式存储单元中的至少一个可以包括开关器件和包括与开关器件并联连接的可变电阻器的数据存储元件。 还讨论了相关设备和制造方法。

    Method of forming a phase change memory device having a small area of contact
    20.
    发明授权
    Method of forming a phase change memory device having a small area of contact 有权
    形成具有小的接触面积的相变存储器件的方法

    公开(公告)号：US07465675B2

    公开(公告)日：2008-12-16

    申请号：US11149499

    申请日：2005-06-09

    申请人： Gwan-Hyeob Koh

    发明人： Gwan-Hyeob Koh

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L45/06 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

    摘要： Methods of fabricating a phase change memory device having a small area of contact are provided. The method includes forming a lower interlayer insulating layer on a semiconductor substrate, and forming a lower conductor pattern within the lower inter-insulating layer. A first insulating layer pattern which crosses a top surface of the lower conductor pattern is formed on the semiconductor substrate having the lower conductor pattern. A conductive spacer pattern electrically connected to the lower conductor pattern is formed on a sidewall of the first insulating layer pattern. A first interlayer insulating layer is formed on the semiconductor substrate having the conductive spacer pattern. The first interlayer insulating layer and the conductive spacer pattern are planarized to form a bottom electrode. A second insulating layer pattern which crosses a top surface of the bottom electrode and exposes a portion of the bottom electrode is formed on the semiconductor substrate having the bottom electrode. A phase change material spacer electrically connected to the bottom electrode is formed on a sidewall of the second insulating layer pattern. A second interlayer insulating layer is formed on the semiconductor substrate having the phase change material spacer. The second interlayer insulating layer and the phase change material spacer are planarized to form a phase change material pattern.

    摘要翻译： 提供了具有小的接触面积的相变存储器件的制造方法。 该方法包括在半导体衬底上形成下层间绝缘层，并在下绝缘层内形成下导体图案。 在具有下导体图案的半导体衬底上形成穿过下导体图案的顶表面的第一绝缘层图案。 电连接到下导体图案的导电间隔物图案形成在第一绝缘层图案的侧壁上。 在具有导电间隔物图案的半导体衬底上形成第一层间绝缘层。 第一层间绝缘层和导电间隔物图案被平坦化以形成底部电极。 在具有底部电极的半导体衬底上形成第二绝缘层图案，该第二绝缘层图案穿过底部电极的顶表面并暴露出底部电极的一部分。 电连接到底部电极的相变材料间隔件形成在第二绝缘层图案的侧壁上。 在具有相变材料间隔物的半导体衬底上形成第二层间绝缘层。 第二层间绝缘层和相变材料间隔物被平坦化以形成相变材料图案。