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    Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same
    13.
    发明授权
    Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same 有权
    具有最初相同的裸片的集成电路芯片堆叠具有开关个性化和制造它们的方法

    公开(公告)号：US08310841B2

    公开(公告)日：2012-11-13

    申请号：US12617273

    申请日：2009-11-12

    申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    IPC分类号： H05K1/11 ,  H05K1/14

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L25/18 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

    摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（TSV）的第二管芯最初相同，所述第一管芯通过在第一管芯上打开开关来个性化， 先前通过开放式开关连接的TSV通过通孔（PTV），每个PTV实现通过第一管芯的导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过打开第二模具上的开关进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

    Method of detecting error in a semiconductor memory device
    14.
    发明申请
    Method of detecting error in a semiconductor memory device 有权
    检测半导体存储器件中的误差的方法

    公开(公告)号：US20110107191A1

    公开(公告)日：2011-05-05

    申请号：US12929250

    申请日：2011-01-11

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays
    16.
    发明申请
    Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays 审中-公开
    包括具有各种单位时间延迟的延迟单元的时间延迟补偿电路

    公开(公告)号：US20080211554A1

    公开(公告)日：2008-09-04

    申请号：US12104997

    申请日：2008-04-17

    申请人： Geun Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

    发明人： Geun Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

    IPC分类号： H03L7/06 ,  H03H11/26

    CPC分类号： H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

    摘要： A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation.

    摘要翻译： 时间延迟补偿电路包括具有各种单位时间延迟的延迟单元。 延迟锁定环路，延时补偿电路的一种类型，包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的多个延迟单元。 响应于预定的移位信号来调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​通过控制外部时钟信号的相位而获得的输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号，该移位信号选择延迟线中的延迟单元的数量。 在延时补偿电路中，用于补偿具有高频率的外部时钟信号的延迟的前延迟单元具有短的单位时间延迟，以便减少由于量化误差引起的抖动。 此外，用于补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟，以便减少延迟补偿所需的延迟单元的数量。

    Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof
    17.
    发明授权
    Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof 失效
    用于内部校正占空比的延迟锁定环路电路和占空比校正方法

    公开(公告)号：US07184509B2

    公开(公告)日：2007-02-27

    申请号：US10619821

    申请日：2003-07-14

    申请人： Geun-Hee Cho ,  Kyu-Hyoun Kim

    发明人： Geun-Hee Cho ,  Kyu-Hyoun Kim

    IPC分类号： H03D3/24 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K5/1565 ,  H03L7/089

    摘要： A delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves the characteristics of a memory device is described. The delay locked loop circuit includes an additional loop for duty cycle correction as well as loops for controlling a rising edge and a falling edge of output signals. Thus, the delay locked loop circuit can internally correct the duty cycle without the use of a phase blender.

    摘要翻译： 具有占空比校正器（DCC）的占空比校正器（DCC）的延迟锁定环路（DCC）具有宽范围的占空比校正，仅消耗少量功率，对工作频率的限制较少，并且提高了存储器件的特性 描述。 延迟锁定环电路包括用于占空比校正的附加回路以及用于控制输出信号的上升沿和下降沿的回路。 因此，延迟锁定环电路可以在不使用相位搅拌器的情况下内部校正占空比。

    Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit
    19.
    发明申请
    Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit 失效
    包括电源的半导体集成电路，包括半导体集成电路的半导体系统和形成半导体集成电路的方法

    公开(公告)号：US20060284302A1

    公开(公告)日：2006-12-21

    申请号：US11447943

    申请日：2006-06-07

    申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

    发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

    IPC分类号： H01L23/52

    CPC分类号： H01L23/58 ,  H01L23/5286 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/83801 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.

    摘要翻译： 提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。 半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。